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target/riscv: set_dcsr_ebreak() while target->state is still changed 

Otherwise it fails.

Fixes #859.

Change-Id: Ib59e6d840316b881481a9b1e01f9d546e73bf932
Signed-off-by: Tim Newsome <tim@sifive.com>
This commit is contained in:
Tim Newsome 2023-06-05 17:24:06 -07:00
parent e0dd44a53c
commit ad89d570e7
1 changed files with 3 additions and 3 deletions
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6
src/target/riscv/riscv-013.c
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@ -1862,9 +1862,6 @@ static int examine(struct target *target)
return ERROR_FAIL;
}
target->state = saved_tgt_state;
target->debug_reason = saved_dbg_reason;
/* Now init registers based on what we discovered. */
if (riscv_init_registers(target) != ERROR_OK)
return ERROR_FAIL;
@ -1872,6 +1869,9 @@ static int examine(struct target *target)
if (update_dcsr(target, false) != ERROR_OK)
return ERROR_FAIL;
target->state = saved_tgt_state;
target->debug_reason = saved_dbg_reason;
if (!halted) {
riscv013_step_or_resume_current_hart(target, false);
target->state = TARGET_RUNNING;