From ad89d570e7b72c265aba39e9080f7a2622af9621 Mon Sep 17 00:00:00 2001 From: Tim Newsome Date: Mon, 5 Jun 2023 17:24:06 -0700 Subject: [PATCH] target/riscv: set_dcsr_ebreak() while target->state is still changed Otherwise it fails. Fixes #859. Change-Id: Ib59e6d840316b881481a9b1e01f9d546e73bf932 Signed-off-by: Tim Newsome --- src/target/riscv/riscv-013.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/target/riscv/riscv-013.c b/src/target/riscv/riscv-013.c index 5f929efab..35b7c9a6d 100644 --- a/src/target/riscv/riscv-013.c +++ b/src/target/riscv/riscv-013.c @@ -1862,9 +1862,6 @@ static int examine(struct target *target) return ERROR_FAIL; } - target->state = saved_tgt_state; - target->debug_reason = saved_dbg_reason; - /* Now init registers based on what we discovered. */ if (riscv_init_registers(target) != ERROR_OK) return ERROR_FAIL; @@ -1872,6 +1869,9 @@ static int examine(struct target *target) if (update_dcsr(target, false) != ERROR_OK) return ERROR_FAIL; + target->state = saved_tgt_state; + target->debug_reason = saved_dbg_reason; + if (!halted) { riscv013_step_or_resume_current_hart(target, false); target->state = TARGET_RUNNING;