Aarch64:Switch to EL1 from EL0 before manipulate MMU
If current core is in EL0, it cannot use 'msr sctlr_el1, x0' Change-Id: I04e60e39e4c84f9d9de7cc87a8e438f5d2737dc3 Signed-off-by: Cheng-Shiun Tsai <cheng.shiun.tsai@gmail.com> Reviewed-on: http://openocd.zylin.com/6051 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
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@ -133,6 +133,7 @@ static int aarch64_mmu_modify(struct target *target, int enable)
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struct aarch64_common *aarch64 = target_to_aarch64(target);
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struct aarch64_common *aarch64 = target_to_aarch64(target);
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struct armv8_common *armv8 = &aarch64->armv8_common;
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struct armv8_common *armv8 = &aarch64->armv8_common;
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int retval = ERROR_OK;
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int retval = ERROR_OK;
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enum arm_mode target_mode = ARM_MODE_ANY;
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uint32_t instr = 0;
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uint32_t instr = 0;
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if (enable) {
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if (enable) {
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@ -158,6 +159,8 @@ static int aarch64_mmu_modify(struct target *target, int enable)
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switch (armv8->arm.core_mode) {
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switch (armv8->arm.core_mode) {
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case ARMV8_64_EL0T:
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case ARMV8_64_EL0T:
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target_mode = ARMV8_64_EL1H;
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/* fall through */
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case ARMV8_64_EL1T:
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case ARMV8_64_EL1T:
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case ARMV8_64_EL1H:
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case ARMV8_64_EL1H:
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instr = ARMV8_MSR_GP(SYSTEM_SCTLR_EL1, 0);
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instr = ARMV8_MSR_GP(SYSTEM_SCTLR_EL1, 0);
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@ -184,9 +187,15 @@ static int aarch64_mmu_modify(struct target *target, int enable)
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LOG_DEBUG("unknown cpu state 0x%x", armv8->arm.core_mode);
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LOG_DEBUG("unknown cpu state 0x%x", armv8->arm.core_mode);
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break;
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break;
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}
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}
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if (target_mode != ARM_MODE_ANY)
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armv8_dpm_modeswitch(&armv8->dpm, target_mode);
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retval = armv8->dpm.instr_write_data_r0(&armv8->dpm, instr,
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retval = armv8->dpm.instr_write_data_r0(&armv8->dpm, instr,
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aarch64->system_control_reg_curr);
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aarch64->system_control_reg_curr);
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if (target_mode != ARM_MODE_ANY)
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armv8_dpm_modeswitch(&armv8->dpm, ARM_MODE_ANY);
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return retval;
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return retval;
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}
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}
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