doc: [3/3] uniform the texinfo syntax for commands definition
To avoid errors in the documentation, like the one fixed by change http://openocd.zylin.com/6134/ , use a uniform notation across the file so simple copy-paste will work. Enclose every command within curly-brackets '{...}', even single word commands. Patch generated through: sed -i 's/^\(@deffn {[^{]*} \)\([^{][^ ]*\)/\1{\2}/' doc/openocd.texi sed -i 's/^\(@deffnx {[^{]*} \)\([^{][^ ]*\)/\1{\2}/' doc/openocd.texi Change-Id: I41a8447d487ec8f6f32c2babcbc73ac21c769344 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/6152 Tested-by: jenkins
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doc/openocd.texi
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doc/openocd.texi
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@ -2063,7 +2063,7 @@ a target has been successfully instantiated.
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If you want to use those commands, you may need to force
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entry to the run stage.
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@deffn {Config Command} init
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@deffn {Config Command} {init}
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This command terminates the configuration stage and
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enters the run stage. This helps when you need to have
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the startup scripts manage tasks such as resetting the target,
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@ -2082,7 +2082,7 @@ read/write memory on your target, @command{init} must occur before
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the memory read/write commands. This includes @command{nand probe}.
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@end deffn
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@deffn {Overridable Procedure} jtag_init
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@deffn {Overridable Procedure} {jtag_init}
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This is invoked at server startup to verify that it can talk
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to the scan chain (list of TAPs) which has been configured.
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@ -2186,13 +2186,13 @@ breakpoints if the memory map has been set up for flash regions.
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@end deffn
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@anchor{gdbflashprogram}
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@deffn {Config Command} gdb_flash_program (@option{enable}|@option{disable})
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@deffn {Config Command} {gdb_flash_program} (@option{enable}|@option{disable})
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Set to @option{enable} to cause OpenOCD to program the flash memory when a
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vFlash packet is received.
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The default behaviour is @option{enable}.
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@end deffn
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@deffn {Config Command} gdb_memory_map (@option{enable}|@option{disable})
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@deffn {Config Command} {gdb_memory_map} (@option{enable}|@option{disable})
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Set to @option{enable} to cause OpenOCD to send the memory configuration to GDB when
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requested. GDB will then know when to set hardware breakpoints, and program flash
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using the GDB load command. @command{gdb_flash_program enable} must also be enabled
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@ -2201,21 +2201,21 @@ Default behaviour is @option{enable}.
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@xref{gdbflashprogram,,gdb_flash_program}.
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@end deffn
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@deffn {Config Command} gdb_report_data_abort (@option{enable}|@option{disable})
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@deffn {Config Command} {gdb_report_data_abort} (@option{enable}|@option{disable})
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Specifies whether data aborts cause an error to be reported
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by GDB memory read packets.
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The default behaviour is @option{disable};
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use @option{enable} see these errors reported.
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@end deffn
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@deffn {Config Command} gdb_report_register_access_error (@option{enable}|@option{disable})
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@deffn {Config Command} {gdb_report_register_access_error} (@option{enable}|@option{disable})
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Specifies whether register accesses requested by GDB register read/write
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packets report errors or not.
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The default behaviour is @option{disable};
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use @option{enable} see these errors reported.
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@end deffn
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@deffn {Config Command} gdb_target_description (@option{enable}|@option{disable})
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@deffn {Config Command} {gdb_target_description} (@option{enable}|@option{disable})
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Set to @option{enable} to cause OpenOCD to send the target descriptions to gdb via qXfer:features:read packet.
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The default behaviour is @option{enable}.
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@end deffn
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@ -2383,7 +2383,7 @@ Specifies either the address of the I/O port (default: 0x378 for LPT1) or
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the number of the @file{/dev/parport} device.
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@end deffn
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@deffn {Config Command} rtck [@option{enable}|@option{disable}]
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@deffn {Config Command} {rtck} [@option{enable}|@option{disable}]
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Displays status of RTCK option.
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Optionally sets that option first.
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@end deffn
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@ -3745,7 +3745,7 @@ schemes. For example, on a multi-target board the standard
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may need the ability to reset only one target at time and
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thus want to avoid using the board-wide SRST signal.
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@deffn {Overridable Procedure} init_reset mode
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@deffn {Overridable Procedure} {init_reset} mode
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This is invoked near the beginning of the @command{reset} command,
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usually to provide as much of a cold (power-up) reset as practical.
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By default it is also invoked from @command{jtag_init} if
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@ -5354,7 +5354,7 @@ As noted above, the @command{flash bank} command requires a driver name,
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and allows driver-specific options and behaviors.
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Some drivers also activate driver-specific commands.
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@deffn {Flash Driver} virtual
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@deffn {Flash Driver} {virtual}
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This is a special driver that maps a previously defined bank to another
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address. All bank settings will be copied from the master physical bank.
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@ -5378,7 +5378,7 @@ flash bank vbank1 virtual 0x9fc00000 0 0 0 \
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@subsection External Flash
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@deffn {Flash Driver} cfi
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@deffn {Flash Driver} {cfi}
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@cindex Common Flash Interface
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@cindex CFI
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The ``Common Flash Interface'' (CFI) is the main standard for
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@ -5423,7 +5423,7 @@ flash bank $_FLASHNAME cfi 0x00000000 0x02000000 2 4 $_TARGETNAME
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@c "cfi part_id" disabled
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@end deffn
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@deffn {Flash Driver} jtagspi
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@deffn {Flash Driver} {jtagspi}
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@cindex Generic JTAG2SPI driver
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@cindex SPI
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@cindex jtagspi
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@ -5464,7 +5464,7 @@ flash bank $_FLASHNAME spi 0x0 0 0 0 \
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@end example
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@end deffn
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@deffn {Flash Driver} xcf
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@deffn {Flash Driver} {xcf}
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@cindex Xilinx Platform flash driver
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@cindex xcf
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Xilinx FPGAs can be configured from specialized flash ICs named Platform Flash.
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@ -5510,7 +5510,7 @@ only "bin" (raw binary, do not confuse it with "bit") and "mcs"
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@end itemize
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@end deffn
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@deffn {Flash Driver} lpcspifi
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@deffn {Flash Driver} {lpcspifi}
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@cindex NXP SPI Flash Interface
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@cindex SPIFI
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@cindex lpcspifi
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@ -5534,7 +5534,7 @@ flash bank $_FLASHNAME lpcspifi 0x14000000 0 0 0 $_TARGETNAME
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@end deffn
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@deffn {Flash Driver} stmsmi
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@deffn {Flash Driver} {stmsmi}
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@cindex STMicroelectronics Serial Memory Interface
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@cindex SMI
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@cindex stmsmi
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@ -5562,7 +5562,7 @@ flash bank $_FLASHNAME stmsmi 0xf8000000 0 0 0 $_TARGETNAME
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@end deffn
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@deffn {Flash Driver} stmqspi
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@deffn {Flash Driver} {stmqspi}
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@cindex STMicroelectronics QuadSPI/OctoSPI Interface
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@cindex QuadSPI
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@cindex OctoSPI
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@ -5677,7 +5677,7 @@ should return the status register contents.
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@end deffn
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@deffn {Flash Driver} mrvlqspi
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@deffn {Flash Driver} {mrvlqspi}
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This driver supports QSPI flash controller of Marvell's Wireless
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Microcontroller platform.
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@ -5690,7 +5690,7 @@ flash bank $_FLASHNAME mrvlqspi 0x0 0 0 0 $_TARGETNAME 0x46010000
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@end deffn
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@deffn {Flash Driver} ath79
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@deffn {Flash Driver} {ath79}
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@cindex Atheros ath79 SPI driver
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@cindex ath79
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Members of ATH79 SoC family from Atheros include a SPI interface with 3
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@ -5729,7 +5729,7 @@ flash bank flash2 ath79 0x20000000 0 0 0 $_TARGETNAME cs2
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@end deffn
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@deffn {Flash Driver} fespi
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@deffn {Flash Driver} {fespi}
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@cindex Freedom E SPI
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@cindex fespi
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@ -5742,7 +5742,7 @@ flash bank $_FLASHNAME fespi 0x20000000 0 0 0 $_TARGETNAME
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@subsection Internal Flash (Microcontrollers)
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@deffn {Flash Driver} aduc702x
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@deffn {Flash Driver} {aduc702x}
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The ADUC702x analog microcontrollers from Analog Devices
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include internal flash and use ARM7TDMI cores.
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The aduc702x flash driver works with models ADUC7019 through ADUC7028.
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@ -5754,7 +5754,7 @@ flash bank $_FLASHNAME aduc702x 0 0 0 0 $_TARGETNAME
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@end example
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@end deffn
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@deffn {Flash Driver} ambiqmicro
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@deffn {Flash Driver} {ambiqmicro}
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@cindex ambiqmicro
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@cindex apollo
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All members of the Apollo microcontroller family from
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@ -5802,7 +5802,7 @@ the flash.
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@end deffn
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@anchor{at91samd}
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@deffn {Flash Driver} at91samd
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@deffn {Flash Driver} {at91samd}
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@cindex at91samd
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All members of the ATSAM D2x, D1x, D0x, ATSAMR, ATSAML and ATSAMC microcontroller
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families from Atmel include internal flash and use ARM's Cortex-M0+ core.
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@ -5891,7 +5891,7 @@ NVMUSERROW: 0xFFFFFC5DD8E0C788
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@end deffn
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@anchor{at91sam3}
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@deffn {Flash Driver} at91sam3
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@deffn {Flash Driver} {at91sam3}
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@cindex at91sam3
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All members of the AT91SAM3 microcontroller family from
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Atmel include internal flash and use ARM's Cortex-M3 core. The driver
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@ -5955,14 +5955,14 @@ This command shows/sets the slow clock frequency used in the
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@end deffn
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@end deffn
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@deffn {Flash Driver} at91sam4
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@deffn {Flash Driver} {at91sam4}
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@cindex at91sam4
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All members of the AT91SAM4 microcontroller family from
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Atmel include internal flash and use ARM's Cortex-M4 core.
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This driver uses the same command names/syntax as @xref{at91sam3}.
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@end deffn
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@deffn {Flash Driver} at91sam4l
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@deffn {Flash Driver} {at91sam4l}
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@cindex at91sam4l
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All members of the AT91SAM4L microcontroller family from
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Atmel include internal flash and use ARM's Cortex-M4 core.
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@ -5977,7 +5977,7 @@ Command is used internally in event reset-deassert-post.
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@end deffn
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@anchor{atsame5}
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@deffn {Flash Driver} atsame5
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@deffn {Flash Driver} {atsame5}
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@cindex atsame5
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All members of the SAM E54, E53, E51 and D51 microcontroller
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families from Microchip (former Atmel) include internal flash
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@ -6040,14 +6040,14 @@ USER PAGE: 0xAEECFF80FE9A9239
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@end deffn
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@deffn {Flash Driver} atsamv
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@deffn {Flash Driver} {atsamv}
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@cindex atsamv
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All members of the ATSAMV7x, ATSAMS70, and ATSAME70 families from
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Atmel include internal flash and use ARM's Cortex-M7 core.
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This driver uses the same command names/syntax as @xref{at91sam3}.
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@end deffn
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@deffn {Flash Driver} at91sam7
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@deffn {Flash Driver} {at91sam7}
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All members of the AT91SAM7 microcontroller family from Atmel include
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internal flash and use ARM7TDMI cores. The driver automatically
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recognizes a number of these chips using the chip identification
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@ -6094,13 +6094,13 @@ the appropriate at91sam7 target.
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@end deffn
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@end deffn
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@deffn {Flash Driver} avr
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@deffn {Flash Driver} {avr}
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The AVR 8-bit microcontrollers from Atmel integrate flash memory.
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@emph{The current implementation is incomplete.}
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@comment - defines mass_erase ... pointless given flash_erase_address
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@end deffn
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@deffn {Flash Driver} bluenrg-x
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@deffn {Flash Driver} {bluenrg-x}
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STMicroelectronics BlueNRG-1, BlueNRG-2 and BlueNRG-LP Bluetooth low energy wireless system-on-chip. They include ARM Cortex-M0/M0+ core and internal flash memory.
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The driver automatically recognizes these chips using
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the chip identification registers, and autoconfigures itself.
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@ -6119,7 +6119,7 @@ flash erase_sector 0 0 last # It will perform a mass erase
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Triggering a mass erase is also useful when users want to disable readout protection.
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@end deffn
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@deffn {Flash Driver} cc26xx
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@deffn {Flash Driver} {cc26xx}
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All versions of the SimpleLink CC13xx and CC26xx microcontrollers from Texas
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Instruments include internal flash. The cc26xx flash driver supports both the
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CC13xx and CC26xx family of devices. The driver automatically recognizes the
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@ -6131,7 +6131,7 @@ flash bank $_FLASHNAME cc26xx 0 0 0 0 $_TARGETNAME
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@end example
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@end deffn
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@deffn {Flash Driver} cc3220sf
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@deffn {Flash Driver} {cc3220sf}
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The CC3220SF version of the SimpleLink CC32xx microcontrollers from Texas
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Instruments includes 1MB of internal flash. The cc3220sf flash driver only
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supports the internal flash. The serial flash on SimpleLink boards is
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@ -6145,7 +6145,7 @@ flash bank $_FLASHNAME cc3220sf 0 0 0 0 $_TARGETNAME
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@end example
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@end deffn
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@deffn {Flash Driver} efm32
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@deffn {Flash Driver} {efm32}
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All members of the EFM32 microcontroller family from Energy Micro include
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internal flash and use ARM Cortex-M3 cores. The driver automatically recognizes
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a number of these chips using the chip identification register, and
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@ -6165,7 +6165,7 @@ Note that in order for this command to take effect, the target needs to be reset
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supported.}
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@end deffn
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@deffn {Flash Driver} esirisc
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@deffn {Flash Driver} {esirisc}
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Members of the eSi-RISC family may optionally include internal flash programmed
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via the eSi-TSMC Flash interface. Additional parameters are required to
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configure the driver: @option{cfg_address} is the base address of the
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@ -6187,7 +6187,7 @@ is an uncommon operation.}
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@end deffn
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@end deffn
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@deffn {Flash Driver} fm3
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@deffn {Flash Driver} {fm3}
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All members of the FM3 microcontroller family from Fujitsu
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include internal flash and use ARM Cortex-M3 cores.
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The @var{fm3} driver uses the @var{target} parameter to select the
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@ -6200,7 +6200,7 @@ flash bank $_FLASHNAME fm3 0 0 0 0 $_TARGETNAME
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@end example
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@end deffn
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@deffn {Flash Driver} fm4
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@deffn {Flash Driver} {fm4}
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All members of the FM4 microcontroller family from Spansion (formerly Fujitsu)
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include internal flash and use ARM Cortex-M4 cores.
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The @var{fm4} driver uses a @var{family} parameter to select the
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@ -6220,7 +6220,7 @@ flash bank $@{_FLASHNAME@}1 fm4 0x00100000 0 0 0 \
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nor is Chip Erase (only Sector Erase is implemented).}
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@end deffn
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@deffn {Flash Driver} kinetis
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@deffn {Flash Driver} {kinetis}
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@cindex kinetis
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Kx, KLx, KVx and KE1x members of the Kinetis microcontroller family
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from NXP (former Freescale) include
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@ -6319,7 +6319,7 @@ Command disables watchdog timer.
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@end deffn
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@end deffn
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@deffn {Flash Driver} kinetis_ke
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@deffn {Flash Driver} {kinetis_ke}
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@cindex kinetis_ke
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KE0x and KEAx members of the Kinetis microcontroller family from NXP include
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internal flash and use ARM Cortex-M0+. The driver automatically recognizes
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@ -6347,7 +6347,7 @@ Command disables watchdog timer.
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@end deffn
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@end deffn
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@deffn {Flash Driver} lpc2000
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@deffn {Flash Driver} {lpc2000}
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This is the driver to support internal flash of all members of the
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LPC11(x)00 and LPC1300 microcontroller families and most members of
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the LPC800, LPC1500, LPC1700, LPC1800, LPC2000, LPC4000, LPC54100,
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@ -6404,7 +6404,7 @@ the specified flash @var{bank}.
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@end deffn
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@end deffn
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@deffn {Flash Driver} lpc288x
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@deffn {Flash Driver} {lpc288x}
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The LPC2888 microcontroller from NXP needs slightly different flash
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support from its lpc2000 siblings.
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The @var{lpc288x} driver defines one mandatory parameter,
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@ -6416,7 +6416,7 @@ flash bank $_FLASHNAME lpc288x 0 0 0 0 $_TARGETNAME 12000000
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@end example
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@end deffn
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@deffn {Flash Driver} lpc2900
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@deffn {Flash Driver} {lpc2900}
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This driver supports the LPC29xx ARM968E based microcontroller family
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from NXP.
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@ -6539,7 +6539,7 @@ lpc2900 secure_jtag 0
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@end deffn
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@end deffn
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@deffn {Flash Driver} mdr
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@deffn {Flash Driver} {mdr}
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This drivers handles the integrated NOR flash on Milandr Cortex-M
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based controllers. A known limitation is that the Info memory can't be
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read or verified as it's not memory mapped.
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@ -6567,7 +6567,7 @@ if @{ [info exists IMEMORY] && [string equal $IMEMORY true] @} @{
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@end example
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@end deffn
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@deffn {Flash Driver} msp432
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@deffn {Flash Driver} {msp432}
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All versions of the SimpleLink MSP432 microcontrollers from Texas
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Instruments include internal flash. The msp432 flash driver automatically
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recognizes the specific version's flash parameters and autoconfigures itself.
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@ -6602,7 +6602,7 @@ msp432 bsl lock
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@end deffn
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@end deffn
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@deffn {Flash Driver} niietcm4
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@deffn {Flash Driver} {niietcm4}
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This drivers handles the integrated NOR flash on NIIET Cortex-M4
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based controllers. Flash size and sector layout are auto-configured by the driver.
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Main flash memory is called "Bootflash" and has main region and info region.
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||||
|
@ -6662,7 +6662,7 @@ Show information about flash driver.
|
|||
|
||||
@end deffn
|
||||
|
||||
@deffn {Flash Driver} nrf5
|
||||
@deffn {Flash Driver} {nrf5}
|
||||
All members of the nRF51 microcontroller families from Nordic Semiconductor
|
||||
include internal flash and use ARM Cortex-M0 core.
|
||||
Also, the nRF52832 microcontroller from Nordic Semiconductor, which include
|
||||
|
@ -6687,7 +6687,7 @@ Decodes and shows information from FICR and UICR registers.
|
|||
|
||||
@end deffn
|
||||
|
||||
@deffn {Flash Driver} ocl
|
||||
@deffn {Flash Driver} {ocl}
|
||||
This driver is an implementation of the ``on chip flash loader''
|
||||
protocol proposed by Pavel Chromy.
|
||||
|
||||
|
@ -6701,7 +6701,7 @@ flash bank $_FLASHNAME ocl 0 0 0 0 $_TARGETNAME
|
|||
@end example
|
||||
@end deffn
|
||||
|
||||
@deffn {Flash Driver} pic32mx
|
||||
@deffn {Flash Driver} {pic32mx}
|
||||
The PIC32MX microcontrollers are based on the MIPS 4K cores,
|
||||
and integrate flash memory.
|
||||
|
||||
|
@ -6725,7 +6725,7 @@ This will remove any Code Protection.
|
|||
@end deffn
|
||||
@end deffn
|
||||
|
||||
@deffn {Flash Driver} psoc4
|
||||
@deffn {Flash Driver} {psoc4}
|
||||
All members of the PSoC 41xx/42xx microcontroller family from Cypress
|
||||
include internal flash and use ARM Cortex-M0 cores.
|
||||
The driver automatically recognizes a number of these chips using
|
||||
|
@ -6759,7 +6759,7 @@ The @var{num} parameter is a value shown by @command{flash banks}.
|
|||
@end deffn
|
||||
@end deffn
|
||||
|
||||
@deffn {Flash Driver} psoc5lp
|
||||
@deffn {Flash Driver} {psoc5lp}
|
||||
All members of the PSoC 5LP microcontroller family from Cypress
|
||||
include internal program flash and use ARM Cortex-M3 cores.
|
||||
The driver probes for a number of these chips and autoconfigures itself,
|
||||
|
@ -6785,7 +6785,7 @@ and all row latches in all flash arrays on the device.
|
|||
@end deffn
|
||||
@end deffn
|
||||
|
||||
@deffn {Flash Driver} psoc5lp_eeprom
|
||||
@deffn {Flash Driver} {psoc5lp_eeprom}
|
||||
All members of the PSoC 5LP microcontroller family from Cypress
|
||||
include internal EEPROM and use ARM Cortex-M3 cores.
|
||||
The driver probes for a number of these chips and autoconfigures itself,
|
||||
|
@ -6797,7 +6797,7 @@ flash bank $_CHIPNAME.eeprom psoc5lp_eeprom 0x40008000 0 0 0 \
|
|||
@end example
|
||||
@end deffn
|
||||
|
||||
@deffn {Flash Driver} psoc5lp_nvl
|
||||
@deffn {Flash Driver} {psoc5lp_nvl}
|
||||
All members of the PSoC 5LP microcontroller family from Cypress
|
||||
include internal Nonvolatile Latches and use ARM Cortex-M3 cores.
|
||||
The driver probes for a number of these chips and autoconfigures itself.
|
||||
|
@ -6822,7 +6822,7 @@ after successful write.
|
|||
@end quotation
|
||||
@end deffn
|
||||
|
||||
@deffn {Flash Driver} psoc6
|
||||
@deffn {Flash Driver} {psoc6}
|
||||
Supports PSoC6 (CY8C6xxx) family of Cypress microcontrollers.
|
||||
PSoC6 is a dual-core device with CM0+ and CM4 cores. Both cores share
|
||||
the same Flash/RAM/MMIO address space.
|
||||
|
@ -6890,7 +6890,7 @@ Note: only Main and Work flash regions support Erase operation.
|
|||
@end deffn
|
||||
@end deffn
|
||||
|
||||
@deffn {Flash Driver} sim3x
|
||||
@deffn {Flash Driver} {sim3x}
|
||||
All members of the SiM3 microcontroller family from Silicon Laboratories
|
||||
include internal flash and use ARM Cortex-M3 cores. It supports both JTAG
|
||||
and SWD interface.
|
||||
|
@ -6913,7 +6913,7 @@ Lock the flash. To unlock use the @command{sim3x mass_erase} command.
|
|||
@end deffn
|
||||
@end deffn
|
||||
|
||||
@deffn {Flash Driver} stellaris
|
||||
@deffn {Flash Driver} {stellaris}
|
||||
All members of the Stellaris LM3Sxxx, LM4x and Tiva C microcontroller
|
||||
families from Texas Instruments include internal flash. The driver
|
||||
automatically recognizes a number of these chips using the chip
|
||||
|
@ -6939,7 +6939,7 @@ applied to all of them.
|
|||
@end deffn
|
||||
@end deffn
|
||||
|
||||
@deffn {Flash Driver} stm32f1x
|
||||
@deffn {Flash Driver} {stm32f1x}
|
||||
All members of the STM32F0, STM32F1 and STM32F3 microcontroller families
|
||||
from STMicroelectronics include internal flash and use ARM Cortex-M0/M3/M4 cores.
|
||||
The driver automatically recognizes a number of these chips using
|
||||
|
@ -7001,7 +7001,7 @@ The @var{num} parameter is a value shown by @command{flash banks}.
|
|||
@end deffn
|
||||
@end deffn
|
||||
|
||||
@deffn {Flash Driver} stm32f2x
|
||||
@deffn {Flash Driver} {stm32f2x}
|
||||
All members of the STM32F2, STM32F4 and STM32F7 microcontroller families from STMicroelectronics
|
||||
include internal flash and use ARM Cortex-M3/M4/M7 cores.
|
||||
The driver automatically recognizes a number of these chips using
|
||||
|
@ -7066,7 +7066,7 @@ The @var{num} parameter is a value shown by @command{flash banks}, @var{optcr2}
|
|||
@end deffn
|
||||
@end deffn
|
||||
|
||||
@deffn {Flash Driver} stm32h7x
|
||||
@deffn {Flash Driver} {stm32h7x}
|
||||
All members of the STM32H7 microcontroller families from STMicroelectronics
|
||||
include internal flash and use ARM Cortex-M7 core.
|
||||
The driver automatically recognizes a number of these chips using
|
||||
|
@ -7134,7 +7134,7 @@ stm32h7x option_write 0 0x20 0x8000000 0x8000000
|
|||
@end deffn
|
||||
@end deffn
|
||||
|
||||
@deffn {Flash Driver} stm32lx
|
||||
@deffn {Flash Driver} {stm32lx}
|
||||
All members of the STM32L0 and STM32L1 microcontroller families from STMicroelectronics
|
||||
include internal flash and use ARM Cortex-M3 and Cortex-M0+ cores.
|
||||
The driver automatically recognizes a number of these chips using
|
||||
|
@ -7174,7 +7174,7 @@ The @var{num} parameter is a value shown by @command{flash banks}.
|
|||
@end deffn
|
||||
@end deffn
|
||||
|
||||
@deffn {Flash Driver} stm32l4x
|
||||
@deffn {Flash Driver} {stm32l4x}
|
||||
All members of the STM32 G0, G4, L4, L4+, L5, WB and WL
|
||||
microcontroller families from STMicroelectronics include internal flash
|
||||
and use ARM Cortex-M0+, M4 and M33 cores.
|
||||
|
@ -7275,7 +7275,7 @@ The @var{num} parameter is a value shown by @command{flash banks}.
|
|||
@end deffn
|
||||
@end deffn
|
||||
|
||||
@deffn {Flash Driver} str7x
|
||||
@deffn {Flash Driver} {str7x}
|
||||
All members of the STR7 microcontroller family from STMicroelectronics
|
||||
include internal flash and use ARM7TDMI cores.
|
||||
The @var{str7x} driver defines one mandatory parameter, @var{variant},
|
||||
|
@ -7292,7 +7292,7 @@ for the specified flash bank.
|
|||
@end deffn
|
||||
@end deffn
|
||||
|
||||
@deffn {Flash Driver} str9x
|
||||
@deffn {Flash Driver} {str9x}
|
||||
Most members of the STR9 microcontroller family from STMicroelectronics
|
||||
include internal flash and use ARM966E cores.
|
||||
The str9 needs the flash controller to be configured using
|
||||
|
@ -7317,7 +7317,7 @@ The @var{num} parameter is a value shown by @command{flash banks}.
|
|||
|
||||
@end deffn
|
||||
|
||||
@deffn {Flash Driver} str9xpec
|
||||
@deffn {Flash Driver} {str9xpec}
|
||||
@cindex str9xpec
|
||||
|
||||
Only use this driver for locking/unlocking the device or configuring the option bytes.
|
||||
|
@ -7412,7 +7412,7 @@ unlock str9 device.
|
|||
|
||||
@end deffn
|
||||
|
||||
@deffn {Flash Driver} swm050
|
||||
@deffn {Flash Driver} {swm050}
|
||||
@cindex swm050
|
||||
All members of the swm050 microcontroller family from Foshan Synwit Tech.
|
||||
|
||||
|
@ -7429,7 +7429,7 @@ Erases the entire flash bank.
|
|||
@end deffn
|
||||
|
||||
|
||||
@deffn {Flash Driver} tms470
|
||||
@deffn {Flash Driver} {tms470}
|
||||
Most members of the TMS470 microcontroller family from Texas Instruments
|
||||
include internal flash and use ARM7TDMI cores.
|
||||
This driver doesn't require the chip and bus width to be specified.
|
||||
|
@ -7450,7 +7450,7 @@ the flash clock.
|
|||
@end deffn
|
||||
@end deffn
|
||||
|
||||
@deffn {Flash Driver} w600
|
||||
@deffn {Flash Driver} {w600}
|
||||
W60x series Wi-Fi SoC from WinnerMicro
|
||||
are designed with ARM Cortex-M3 and have 1M Byte QFLASH inside.
|
||||
The @var{w600} driver uses the @var{target} parameter to select the
|
||||
|
@ -7461,12 +7461,12 @@ flash bank $_FLASHNAME w600 0x08000000 0 0 0 $_TARGETNAMEs
|
|||
@end example
|
||||
@end deffn
|
||||
|
||||
@deffn {Flash Driver} xmc1xxx
|
||||
@deffn {Flash Driver} {xmc1xxx}
|
||||
All members of the XMC1xxx microcontroller family from Infineon.
|
||||
This driver does not require the chip and bus width to be specified.
|
||||
@end deffn
|
||||
|
||||
@deffn {Flash Driver} xmc4xxx
|
||||
@deffn {Flash Driver} {xmc4xxx}
|
||||
All members of the XMC4xxx microcontroller family from Infineon.
|
||||
This driver does not require the chip and bus width to be specified.
|
||||
|
||||
|
@ -7794,7 +7794,7 @@ As noted above, the @command{nand device} command allows
|
|||
driver-specific options and behaviors.
|
||||
Some controllers also activate controller-specific commands.
|
||||
|
||||
@deffn {NAND Driver} at91sam9
|
||||
@deffn {NAND Driver} {at91sam9}
|
||||
This driver handles the NAND controllers found on AT91SAM9 family chips from
|
||||
Atmel. It takes two extra parameters: address of the NAND chip;
|
||||
address of the ECC controller.
|
||||
|
@ -7829,7 +7829,7 @@ is the base address of the PIO controller and @var{pin} is the pin number.
|
|||
@end deffn
|
||||
@end deffn
|
||||
|
||||
@deffn {NAND Driver} davinci
|
||||
@deffn {NAND Driver} {davinci}
|
||||
This driver handles the NAND controllers found on DaVinci family
|
||||
chips from Texas Instruments.
|
||||
It takes three extra parameters:
|
||||
|
@ -7847,7 +7847,7 @@ to implement those ECC modes, unless they are disabled using
|
|||
the @command{nand raw_access} command.
|
||||
@end deffn
|
||||
|
||||
@deffn {NAND Driver} lpc3180
|
||||
@deffn {NAND Driver} {lpc3180}
|
||||
These controllers require an extra @command{nand device}
|
||||
parameter: the clock rate used by the controller.
|
||||
@deffn {Command} {lpc3180 select} num [mlc|slc]
|
||||
|
@ -7863,12 +7863,12 @@ in the MLC controller mode, but won't change SLC behavior.
|
|||
@end deffn
|
||||
@comment current lpc3180 code won't issue 5-byte address cycles
|
||||
|
||||
@deffn {NAND Driver} mx3
|
||||
@deffn {NAND Driver} {mx3}
|
||||
This driver handles the NAND controller in i.MX31. The mxc driver
|
||||
should work for this chip as well.
|
||||
@end deffn
|
||||
|
||||
@deffn {NAND Driver} mxc
|
||||
@deffn {NAND Driver} {mxc}
|
||||
This driver handles the NAND controller found in Freescale i.MX
|
||||
chips. It has support for v1 (i.MX27 and i.MX31) and v2 (i.MX35).
|
||||
The driver takes 3 extra arguments, chip (@option{mx27},
|
||||
|
@ -7884,7 +7884,7 @@ without parameter query status.
|
|||
@end deffn
|
||||
@end deffn
|
||||
|
||||
@deffn {NAND Driver} orion
|
||||
@deffn {NAND Driver} {orion}
|
||||
These controllers require an extra @command{nand device}
|
||||
parameter: the address of the controller.
|
||||
@example
|
||||
|
@ -7896,11 +7896,11 @@ or @code{read_page} methods, so @command{nand raw_access} won't
|
|||
change any behavior.
|
||||
@end deffn
|
||||
|
||||
@deffn {NAND Driver} s3c2410
|
||||
@deffnx {NAND Driver} s3c2412
|
||||
@deffnx {NAND Driver} s3c2440
|
||||
@deffnx {NAND Driver} s3c2443
|
||||
@deffnx {NAND Driver} s3c6400
|
||||
@deffn {NAND Driver} {s3c2410}
|
||||
@deffnx {NAND Driver} {s3c2412}
|
||||
@deffnx {NAND Driver} {s3c2440}
|
||||
@deffnx {NAND Driver} {s3c2443}
|
||||
@deffnx {NAND Driver} {s3c6400}
|
||||
These S3C family controllers don't have any special
|
||||
@command{nand device} options, and don't define any
|
||||
specialized commands.
|
||||
|
@ -7987,7 +7987,7 @@ Drivers may support PLD-specific options to the @command{pld device}
|
|||
definition command, and may also define commands usable only with
|
||||
that particular type of PLD.
|
||||
|
||||
@deffn {FPGA Driver} virtex2 [no_jstart]
|
||||
@deffn {FPGA Driver} {virtex2} [no_jstart]
|
||||
Virtex-II is a family of FPGAs sold by Xilinx.
|
||||
It supports the IEEE 1532 standard for In-System Configuration (ISC).
|
||||
|
||||
|
@ -8756,7 +8756,7 @@ Stops trace data collection.
|
|||
|
||||
To use an ETM trace port it must be associated with a driver.
|
||||
|
||||
@deffn {Trace Port Driver} dummy
|
||||
@deffn {Trace Port Driver} {dummy}
|
||||
Use the @option{dummy} driver if you are configuring an ETM that's
|
||||
not connected to anything (on-chip ETB or off-chip trace connector).
|
||||
@emph{This driver lets OpenOCD talk to the ETM, but it does not expose
|
||||
|
@ -8766,7 +8766,7 @@ Associates the ETM for @var{target} with a dummy driver.
|
|||
@end deffn
|
||||
@end deffn
|
||||
|
||||
@deffn {Trace Port Driver} etb
|
||||
@deffn {Trace Port Driver} {etb}
|
||||
Use the @option{etb} driver if you are configuring an ETM
|
||||
to use on-chip ETB memory.
|
||||
@deffn {Config Command} {etb config} target etb_tap
|
||||
|
|
Loading…
Reference in New Issue