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target/riscv: read registers are not valid on a running target 

Change-Id: I2c5335bb6055b767d3c3ffb3f6910b71b9c2bb35
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
This commit is contained in:
Evgeniy Naydanov 2024-04-03 16:42:14 +03:00
parent 722cef1ae0
commit 9c45c9f4be
1 changed files with 2 additions and 1 deletions
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src/target/riscv/riscv.c
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@ -5260,7 +5260,8 @@ int riscv_get_register(struct target *target, riscv_reg_t *value,
return ERROR_FAIL; return ERROR_FAIL;
buf_set_u64(reg->value, 0, reg->size, *value); buf_set_u64(reg->value, 0, reg->size, *value);
reg->valid = gdb_regno_cacheable(regid, /* is write? */ false); reg->valid = gdb_regno_cacheable(regid, /* is write? */ false) &&
target->state == TARGET_HALTED;
reg->dirty = false; reg->dirty = false;
LOG_TARGET_DEBUG(target, "Read %s: 0x%" PRIx64, reg->name, *value); LOG_TARGET_DEBUG(target, "Read %s: 0x%" PRIx64, reg->name, *value);