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Merge pull request #1022 from en-sc/en-sc/upstream-refactor-reg-acc 

[NFC] target/riscv: refactor `init_registers()`
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Evgeniy Naydanov 2024-03-27 20:10:10 +03:00 committed by GitHub
parent cb2b394514 ea7e17491d
commit 722cef1ae0
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GPG Key ID: B5690EEEBB952194
3 changed files with 535 additions and 385 deletions
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5
src/target/riscv/gdb_regs.h
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@ -78,6 +78,9 @@ enum gdb_regno {
GDB_REGNO_FT11,
GDB_REGNO_FPR31 = GDB_REGNO_FT11,
GDB_REGNO_CSR0 = 65,
GDB_REGNO_FCSR = CSR_FCSR + GDB_REGNO_CSR0,
GDB_REGNO_FFLAGS = CSR_FFLAGS + GDB_REGNO_CSR0,
GDB_REGNO_FRM = CSR_FRM + GDB_REGNO_CSR0,
GDB_REGNO_VSTART = CSR_VSTART + GDB_REGNO_CSR0,
GDB_REGNO_VXSAT = CSR_VXSAT + GDB_REGNO_CSR0,
GDB_REGNO_VXRM = CSR_VXRM + GDB_REGNO_CSR0,
@ -120,6 +123,6 @@ enum gdb_regno {
GDB_REGNO_COUNT
};
const char *gdb_regno_name(struct target *target, enum gdb_regno regno);
const char *gdb_regno_name(const struct target *target, enum gdb_regno regno);
#endif

907
src/target/riscv/riscv.c
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File diff suppressed because it is too large Load Diff

8
src/target/riscv/riscv.h
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@ -260,6 +260,9 @@ struct riscv_info {
COMMAND_HELPER((*print_info), struct target *target);
/* Storage for arch_info of non-custom registers. */
riscv_reg_info_t shared_reg_info;
/* Storage for vector register types. */
struct reg_data_type_vector vector_uint8;
struct reg_data_type_vector vector_uint16;
@ -390,11 +393,14 @@ int riscv_openocd_step(
/*** RISC-V Interface ***/
bool riscv_supports_extension(struct target *target, char letter);
bool riscv_supports_extension(const struct target *target, char letter);
/* Returns XLEN for the given (or current) hart. */
unsigned riscv_xlen(const struct target *target);
/* Returns VLENB for the given (or current) hart. */
unsigned int riscv_vlenb(const struct target *target);
/*** Support functions for the RISC-V 'RTOS', which provides multihart support
* without requiring multiple targets. */