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target/riscv: Add target logging to most logging instances 

This patch adds target logging to logging instances where it makes sense.
This is especially useful when debugging multiple targets at once,
such as multicore systems.

Change-Id: Ia9861f3fa0e6e5908b683c2a8280659c3c264395
Signed-off-by: Marek Vrbka <marek.vrbka@codasip.com>
This commit is contained in:
Marek Vrbka 2023-07-11 10:54:58 +02:00
parent 21fd3e1d6c
commit 9036f4003a
4 changed files with 269 additions and 270 deletions
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4
src/target/riscv/batch.c
View File

@ -88,7 +88,7 @@ bool riscv_batch_full(struct riscv_batch *batch)
int riscv_batch_run(struct riscv_batch *batch) int riscv_batch_run(struct riscv_batch *batch)
{ {
if (batch->used_scans == 0) { if (batch->used_scans == 0) {
LOG_DEBUG("Ignoring empty batch."); LOG_TARGET_DEBUG(batch->target, "Ignoring empty batch.");
return ERROR_OK; return ERROR_OK;
} }
@ -107,7 +107,7 @@ int riscv_batch_run(struct riscv_batch *batch)
keep_alive(); keep_alive();
if (jtag_execute_queue() != ERROR_OK) { if (jtag_execute_queue() != ERROR_OK) {
LOG_ERROR("Unable to execute JTAG queue"); LOG_TARGET_ERROR(batch->target, "Unable to execute JTAG queue");
return ERROR_FAIL; return ERROR_FAIL;
} }

250
src/target/riscv/riscv-013.c
View File

@ -247,7 +247,7 @@ static dm013_info_t *get_dm(struct target *target)
} }
if (!dm) { if (!dm) {
LOG_DEBUG("[%d] Allocating new DM", target->coreid); LOG_TARGET_DEBUG(target, "Coreid [%d] Allocating new DM", target->coreid);
dm = calloc(1, sizeof(dm013_info_t)); dm = calloc(1, sizeof(dm013_info_t));
if (!dm) if (!dm)
return NULL; return NULL;
@ -457,7 +457,7 @@ static void increase_dmi_busy_delay(struct target *target)
{ {
riscv013_info_t *info = get_info(target); riscv013_info_t *info = get_info(target);
info->dmi_busy_delay += info->dmi_busy_delay / 10 + 1; info->dmi_busy_delay += info->dmi_busy_delay / 10 + 1;
LOG_DEBUG("dtmcs_idle=%d, dmi_busy_delay=%d, ac_busy_delay=%d", LOG_TARGET_DEBUG(target, "dtmcs_idle=%d, dmi_busy_delay=%d, ac_busy_delay=%d",
info->dtmcs_idle, info->dmi_busy_delay, info->dtmcs_idle, info->dmi_busy_delay,
info->ac_busy_delay); info->ac_busy_delay);
@ -656,10 +656,10 @@ static int dmi_op(struct target *target, uint32_t *data_in,
int result = dmi_op_timeout(target, data_in, dmi_busy_encountered, dmi_op, int result = dmi_op_timeout(target, data_in, dmi_busy_encountered, dmi_op,
address, data_out, riscv_command_timeout_sec, exec, ensure_success); address, data_out, riscv_command_timeout_sec, exec, ensure_success);
if (result == ERROR_TIMEOUT_REACHED) { if (result == ERROR_TIMEOUT_REACHED) {
LOG_ERROR("[%s] DMI operation didn't complete in %d seconds. The target is " LOG_TARGET_ERROR(target, "DMI operation didn't complete in %d seconds. The target is "
"either really slow or broken. You could increase the " "either really slow or broken. You could increase the "
"timeout with riscv set_command_timeout_sec.", "timeout with riscv set_command_timeout_sec.",
target_name(target), riscv_command_timeout_sec); riscv_command_timeout_sec);
return ERROR_FAIL; return ERROR_FAIL;
} }
return result; return result;
@ -725,7 +725,7 @@ static void increase_ac_busy_delay(struct target *target)
{ {
riscv013_info_t *info = get_info(target); riscv013_info_t *info = get_info(target);
info->ac_busy_delay += info->ac_busy_delay / 10 + 1; info->ac_busy_delay += info->ac_busy_delay / 10 + 1;
LOG_DEBUG("dtmcs_idle=%d, dmi_busy_delay=%d, ac_busy_delay=%d", LOG_TARGET_DEBUG(target, "dtmcs_idle=%d, dmi_busy_delay=%d, ac_busy_delay=%d",
info->dtmcs_idle, info->dmi_busy_delay, info->dtmcs_idle, info->dmi_busy_delay,
info->ac_busy_delay); info->ac_busy_delay);
} }
@ -759,7 +759,7 @@ static int wait_for_idle(struct target *target, uint32_t *abstractcs)
if (time(NULL) - start > riscv_command_timeout_sec) { if (time(NULL) - start > riscv_command_timeout_sec) {
info->cmderr = get_field(*abstractcs, DM_ABSTRACTCS_CMDERR); info->cmderr = get_field(*abstractcs, DM_ABSTRACTCS_CMDERR);
LOG_ERROR("Timed out after %ds waiting for busy to go low (abstractcs=0x%x). " LOG_TARGET_ERROR(target, "Timed out after %ds waiting for busy to go low (abstractcs=0x%x). "
"Increase the timeout with riscv set_command_timeout_sec.", "Increase the timeout with riscv set_command_timeout_sec.",
riscv_command_timeout_sec, riscv_command_timeout_sec,
*abstractcs); *abstractcs);
@ -780,7 +780,7 @@ static int execute_abstract_command(struct target *target, uint32_t command)
if (debug_level >= LOG_LVL_DEBUG) { if (debug_level >= LOG_LVL_DEBUG) {
switch (get_field(command, DM_COMMAND_CMDTYPE)) { switch (get_field(command, DM_COMMAND_CMDTYPE)) {
case 0: case 0:
LOG_DEBUG("command=0x%x; access register, size=%d, postexec=%d, " LOG_TARGET_DEBUG(target, "command=0x%x; access register, size=%d, postexec=%d, "
"transfer=%d, write=%d, regno=0x%x", "transfer=%d, write=%d, regno=0x%x",
command, command,
8 << get_field(command, AC_ACCESS_REGISTER_AARSIZE), 8 << get_field(command, AC_ACCESS_REGISTER_AARSIZE),
@ -790,7 +790,7 @@ static int execute_abstract_command(struct target *target, uint32_t command)
get_field(command, AC_ACCESS_REGISTER_REGNO)); get_field(command, AC_ACCESS_REGISTER_REGNO));
break; break;
default: default:
LOG_DEBUG("command=0x%x", command); LOG_TARGET_DEBUG(target, "command=0x%x", command);
break; break;
} }
} }
@ -803,7 +803,7 @@ static int execute_abstract_command(struct target *target, uint32_t command)
info->cmderr = get_field(abstractcs, DM_ABSTRACTCS_CMDERR); info->cmderr = get_field(abstractcs, DM_ABSTRACTCS_CMDERR);
if (info->cmderr != 0 || result != ERROR_OK) { if (info->cmderr != 0 || result != ERROR_OK) {
LOG_DEBUG("command 0x%x failed; abstractcs=0x%x", command, abstractcs); LOG_TARGET_DEBUG(target, "command 0x%x failed; abstractcs=0x%x", command, abstractcs);
/* Clear the error. */ /* Clear the error. */
dmi_write(target, DM_ABSTRACTCS, DM_ABSTRACTCS_CMDERR); dmi_write(target, DM_ABSTRACTCS, DM_ABSTRACTCS_CMDERR);
return ERROR_FAIL; return ERROR_FAIL;
@ -820,7 +820,7 @@ static riscv_reg_t read_abstract_arg(struct target *target, unsigned index,
unsigned offset = index * size_bits / 32; unsigned offset = index * size_bits / 32;
switch (size_bits) { switch (size_bits) {
default: default:
LOG_ERROR("Unsupported size: %d bits", size_bits); LOG_TARGET_ERROR(target, "Unsupported size: %d bits", size_bits);
return ~0; return ~0;
case 64: case 64:
dmi_read(target, &v, DM_DATA0 + offset + 1); dmi_read(target, &v, DM_DATA0 + offset + 1);
@ -839,7 +839,7 @@ static int write_abstract_arg(struct target *target, unsigned index,
unsigned offset = index * size_bits / 32; unsigned offset = index * size_bits / 32;
switch (size_bits) { switch (size_bits) {
default: default:
LOG_ERROR("Unsupported size: %d bits", size_bits); LOG_TARGET_ERROR(target, "Unsupported size: %d bits", size_bits);
return ERROR_FAIL; return ERROR_FAIL;
case 64: case 64:
dmi_write(target, DM_DATA0 + offset + 1, value >> 32); dmi_write(target, DM_DATA0 + offset + 1, value >> 32);
@ -865,8 +865,8 @@ static uint32_t access_register_command(struct target *target, uint32_t number,
command = set_field(command, AC_ACCESS_REGISTER_AARSIZE, 3); command = set_field(command, AC_ACCESS_REGISTER_AARSIZE, 3);
break; break;
default: default:
LOG_ERROR("[%s] %d-bit register %s not supported.", LOG_TARGET_ERROR(target, "%d-bit register %s not supported.",
target_name(target), size, gdb_regno_name(number)); size, gdb_regno_name(number));
assert(0); assert(0);
} }
@ -918,10 +918,10 @@ static int register_read_abstract_with_size(struct target *target,
if (info->cmderr == CMDERR_NOT_SUPPORTED) { if (info->cmderr == CMDERR_NOT_SUPPORTED) {
if (number >= GDB_REGNO_FPR0 && number <= GDB_REGNO_FPR31) { if (number >= GDB_REGNO_FPR0 && number <= GDB_REGNO_FPR31) {
info->abstract_read_fpr_supported = false; info->abstract_read_fpr_supported = false;
LOG_INFO("Disabling abstract command reads from FPRs."); LOG_TARGET_INFO(target, "Disabling abstract command reads from FPRs.");
} else if (number >= GDB_REGNO_CSR0 && number <= GDB_REGNO_CSR4095) { } else if (number >= GDB_REGNO_CSR0 && number <= GDB_REGNO_CSR4095) {
info->abstract_read_csr_supported = false; info->abstract_read_csr_supported = false;
LOG_INFO("Disabling abstract command reads from CSRs."); LOG_TARGET_INFO(target, "Disabling abstract command reads from CSRs.");
} }
} }
return result; return result;
@ -966,10 +966,10 @@ static int register_write_abstract(struct target *target, enum gdb_regno number,
if (info->cmderr == CMDERR_NOT_SUPPORTED) { if (info->cmderr == CMDERR_NOT_SUPPORTED) {
if (number >= GDB_REGNO_FPR0 && number <= GDB_REGNO_FPR31) { if (number >= GDB_REGNO_FPR0 && number <= GDB_REGNO_FPR31) {
info->abstract_write_fpr_supported = false; info->abstract_write_fpr_supported = false;
LOG_INFO("Disabling abstract command writes to FPRs."); LOG_TARGET_INFO(target, "Disabling abstract command writes to FPRs.");
} else if (number >= GDB_REGNO_CSR0 && number <= GDB_REGNO_CSR4095) { } else if (number >= GDB_REGNO_CSR0 && number <= GDB_REGNO_CSR4095) {
info->abstract_write_csr_supported = false; info->abstract_write_csr_supported = false;
LOG_INFO("Disabling abstract command writes to CSRs."); LOG_TARGET_INFO(target, "Disabling abstract command writes to CSRs.");
} }
} }
return result; return result;
@ -1028,7 +1028,7 @@ static int examine_progbuf(struct target *target)
if (info->progbufsize < 1) { if (info->progbufsize < 1) {
info->progbuf_writable = YNM_NO; info->progbuf_writable = YNM_NO;
LOG_INFO("No program buffer present."); LOG_TARGET_INFO(target, "No program buffer present.");
return ERROR_OK; return ERROR_OK;
} }
@ -1059,12 +1059,12 @@ static int examine_progbuf(struct target *target)
if (dmi_read(target, &written, DM_PROGBUF0) != ERROR_OK) if (dmi_read(target, &written, DM_PROGBUF0) != ERROR_OK)
return ERROR_FAIL; return ERROR_FAIL;
if (written == (uint32_t) info->progbuf_address) { if (written == (uint32_t) info->progbuf_address) {
LOG_INFO("progbuf is writable at 0x%" PRIx64, LOG_TARGET_INFO(target, "progbuf is writable at 0x%" PRIx64,
info->progbuf_address); info->progbuf_address);
info->progbuf_writable = YNM_YES; info->progbuf_writable = YNM_YES;
} else { } else {
LOG_INFO("progbuf is not writeable at 0x%" PRIx64, LOG_TARGET_INFO(target, "progbuf is not writeable at 0x%" PRIx64,
info->progbuf_address); info->progbuf_address);
info->progbuf_writable = YNM_NO; info->progbuf_writable = YNM_NO;
} }
@ -1212,7 +1212,7 @@ static int scratch_reserve(struct target *target,
return ERROR_OK; return ERROR_OK;
} }
LOG_ERROR("Couldn't find %d bytes of scratch RAM to use. Please configure " LOG_TARGET_ERROR(target, "Couldn't find %d bytes of scratch RAM to use. Please configure "
"a work area with 'configure -work-area-phys'.", size_bytes); "a work area with 'configure -work-area-phys'.", size_bytes);
return ERROR_FAIL; return ERROR_FAIL;
} }
@ -1380,7 +1380,7 @@ static int register_read_progbuf(struct target *target, uint64_t *value,
if (riscv_program_csrr(&program, S0, number) != ERROR_OK) if (riscv_program_csrr(&program, S0, number) != ERROR_OK)
return ERROR_FAIL; return ERROR_FAIL;
} else { } else {
LOG_ERROR("Unsupported register: %s", gdb_regno_name(number)); LOG_TARGET_ERROR(target, "Unsupported register: %s", gdb_regno_name(number));
return ERROR_FAIL; return ERROR_FAIL;
} }
@ -1480,7 +1480,7 @@ static int register_write_progbuf(struct target *target, enum gdb_regno number,
if (riscv_program_csrw(&program, S0, number) != ERROR_OK) if (riscv_program_csrw(&program, S0, number) != ERROR_OK)
return ERROR_FAIL; return ERROR_FAIL;
} else { } else {
LOG_ERROR("Unsupported register (enum gdb_regno)(%d)", number); LOG_TARGET_ERROR(target, "Unsupported register (enum gdb_regno)(%d)", number);
return ERROR_FAIL; return ERROR_FAIL;
} }
return riscv_program_exec(&program, target); return riscv_program_exec(&program, target);
@ -1559,7 +1559,7 @@ static int wait_for_authbusy(struct target *target, uint32_t *dmstatus)
if (!get_field(value, DM_DMSTATUS_AUTHBUSY)) if (!get_field(value, DM_DMSTATUS_AUTHBUSY))
break; break;
if (time(NULL) - start > riscv_command_timeout_sec) { if (time(NULL) - start > riscv_command_timeout_sec) {
LOG_ERROR("Timed out after %ds waiting for authbusy to go low (dmstatus=0x%x). " LOG_TARGET_ERROR(target, "Timed out after %ds waiting for authbusy to go low (dmstatus=0x%x). "
"Increase the timeout with riscv set_command_timeout_sec.", "Increase the timeout with riscv set_command_timeout_sec.",
riscv_command_timeout_sec, riscv_command_timeout_sec,
value); value);
@ -1663,7 +1663,7 @@ static int halt_set_dcsr_ebreak(struct target *target)
static void deinit_target(struct target *target) static void deinit_target(struct target *target)
{ {
LOG_DEBUG("riscv_deinit_target()"); LOG_TARGET_DEBUG(target, "Deinitializing target.");
struct riscv_info *info = target->arch_info; struct riscv_info *info = target->arch_info;
if (!info) if (!info)
return; return;
@ -1695,19 +1695,19 @@ static int examine(struct target *target)
/* Don't need to select dbus, since the first thing we do is read dtmcontrol. */ /* Don't need to select dbus, since the first thing we do is read dtmcontrol. */
uint32_t dtmcontrol = dtmcontrol_scan(target, 0); uint32_t dtmcontrol = dtmcontrol_scan(target, 0);
LOG_DEBUG("dtmcontrol=0x%x", dtmcontrol); LOG_TARGET_DEBUG(target, "dtmcontrol=0x%x", dtmcontrol);
LOG_DEBUG(" dmireset=%d", get_field(dtmcontrol, DTM_DTMCS_DMIRESET)); LOG_TARGET_DEBUG(target, " dmireset=%d", get_field(dtmcontrol, DTM_DTMCS_DMIRESET));
LOG_DEBUG(" idle=%d", get_field(dtmcontrol, DTM_DTMCS_IDLE)); LOG_TARGET_DEBUG(target, " idle=%d", get_field(dtmcontrol, DTM_DTMCS_IDLE));
LOG_DEBUG(" dmistat=%d", get_field(dtmcontrol, DTM_DTMCS_DMISTAT)); LOG_TARGET_DEBUG(target, " dmistat=%d", get_field(dtmcontrol, DTM_DTMCS_DMISTAT));
LOG_DEBUG(" abits=%d", get_field(dtmcontrol, DTM_DTMCS_ABITS)); LOG_TARGET_DEBUG(target, " abits=%d", get_field(dtmcontrol, DTM_DTMCS_ABITS));
LOG_DEBUG(" version=%d", get_field(dtmcontrol, DTM_DTMCS_VERSION)); LOG_TARGET_DEBUG(target, " version=%d", get_field(dtmcontrol, DTM_DTMCS_VERSION));
if (dtmcontrol == 0) { if (dtmcontrol == 0) {
LOG_ERROR("dtmcontrol is 0. Check JTAG connectivity/board power."); LOG_TARGET_ERROR(target, "dtmcontrol is 0. Check JTAG connectivity/board power.");
return ERROR_FAIL; return ERROR_FAIL;
} }
if (get_field(dtmcontrol, DTM_DTMCS_VERSION) != 1) { if (get_field(dtmcontrol, DTM_DTMCS_VERSION) != 1) {
LOG_ERROR("[%s] Unsupported DTM version %d. (dtmcontrol=0x%x)", LOG_TARGET_ERROR(target, "Unsupported DTM version %d. (dtmcontrol=0x%x)",
target_name(target), get_field(dtmcontrol, DTM_DTMCS_VERSION), dtmcontrol); get_field(dtmcontrol, DTM_DTMCS_VERSION), dtmcontrol);
return ERROR_FAIL; return ERROR_FAIL;
} }
@ -1743,7 +1743,7 @@ static int examine(struct target *target)
if (!get_field(dmcontrol, DM_DMCONTROL_DMACTIVE)) { if (!get_field(dmcontrol, DM_DMCONTROL_DMACTIVE)) {
LOG_ERROR("Debug Module did not become active. dmcontrol=0x%x", LOG_TARGET_ERROR(target, "Debug Module did not become active. dmcontrol=0x%x",
dmcontrol); dmcontrol);
return ERROR_FAIL; return ERROR_FAIL;
} }
@ -1753,7 +1753,7 @@ static int examine(struct target *target)
uint32_t dmstatus; uint32_t dmstatus;
if (dmstatus_read(target, &dmstatus, false) != ERROR_OK) if (dmstatus_read(target, &dmstatus, false) != ERROR_OK)
return ERROR_FAIL; return ERROR_FAIL;
LOG_DEBUG("dmstatus: 0x%08x", dmstatus); LOG_TARGET_DEBUG(target, "dmstatus: 0x%08x", dmstatus);
int dmstatus_version = get_field(dmstatus, DM_DMSTATUS_VERSION); int dmstatus_version = get_field(dmstatus, DM_DMSTATUS_VERSION);
if (dmstatus_version != 2 && dmstatus_version != 3) { if (dmstatus_version != 2 && dmstatus_version != 3) {
/* Error was already printed out in dmstatus_read(). */ /* Error was already printed out in dmstatus_read(). */
@ -1769,7 +1769,7 @@ static int examine(struct target *target)
info->hartsellen++; info->hartsellen++;
hartsel >>= 1; hartsel >>= 1;
} }
LOG_DEBUG("hartsellen=%d", info->hartsellen); LOG_TARGET_DEBUG(target, "hartsellen=%d", info->hartsellen);
uint32_t hartinfo; uint32_t hartinfo;
if (dmi_read(target, &hartinfo, DM_HARTINFO) != ERROR_OK) if (dmi_read(target, &hartinfo, DM_HARTINFO) != ERROR_OK)
@ -1780,7 +1780,7 @@ static int examine(struct target *target)
info->dataaddr = get_field(hartinfo, DM_HARTINFO_DATAADDR); info->dataaddr = get_field(hartinfo, DM_HARTINFO_DATAADDR);
if (!get_field(dmstatus, DM_DMSTATUS_AUTHENTICATED)) { if (!get_field(dmstatus, DM_DMSTATUS_AUTHENTICATED)) {
LOG_ERROR("Debugger is not authenticated to target Debug Module. " LOG_TARGET_ERROR(target, "Debugger is not authenticated to target Debug Module. "
"(dmstatus=0x%x). Use `riscv authdata_read` and " "(dmstatus=0x%x). Use `riscv authdata_read` and "
"`riscv authdata_write` commands to authenticate.", dmstatus); "`riscv authdata_write` commands to authenticate.", dmstatus);
return ERROR_FAIL; return ERROR_FAIL;
@ -1796,21 +1796,21 @@ static int examine(struct target *target)
info->datacount = get_field(abstractcs, DM_ABSTRACTCS_DATACOUNT); info->datacount = get_field(abstractcs, DM_ABSTRACTCS_DATACOUNT);
info->progbufsize = get_field(abstractcs, DM_ABSTRACTCS_PROGBUFSIZE); info->progbufsize = get_field(abstractcs, DM_ABSTRACTCS_PROGBUFSIZE);
LOG_INFO("[%s] datacount=%d progbufsize=%d", target_name(target), LOG_TARGET_INFO(target, "datacount=%d progbufsize=%d",
info->datacount, info->progbufsize); info->datacount, info->progbufsize);
RISCV_INFO(r); RISCV_INFO(r);
r->impebreak = get_field(dmstatus, DM_DMSTATUS_IMPEBREAK); r->impebreak = get_field(dmstatus, DM_DMSTATUS_IMPEBREAK);
if (!has_sufficient_progbuf(target, 2)) { if (!has_sufficient_progbuf(target, 2)) {
LOG_WARNING("We won't be able to execute fence instructions on this " LOG_TARGET_WARNING(target, "We won't be able to execute fence instructions on this "
"target. Memory may not always appear consistent. " "target. Memory may not always appear consistent. "
"(progbufsize=%d, impebreak=%d)", info->progbufsize, "(progbufsize=%d, impebreak=%d)", info->progbufsize,
r->impebreak); r->impebreak);
} }
if (info->progbufsize < 4 && riscv_enable_virtual) { if (info->progbufsize < 4 && riscv_enable_virtual) {
LOG_ERROR("set_enable_virtual is not available on this target. It " LOG_TARGET_ERROR(target, "set_enable_virtual is not available on this target. It "
"requires a program buffer size of at least 4. (progbufsize=%d) " "requires a program buffer size of at least 4. (progbufsize=%d) "
"Use `riscv set_enable_virtual off` to continue." "Use `riscv set_enable_virtual off` to continue."
, info->progbufsize); , info->progbufsize);
@ -1834,11 +1834,11 @@ static int examine(struct target *target)
set_dmcontrol_hartsel(DM_DMCONTROL_DMACTIVE | DM_DMCONTROL_ACKHAVERESET, i)); set_dmcontrol_hartsel(DM_DMCONTROL_DMACTIVE | DM_DMCONTROL_ACKHAVERESET, i));
} }
LOG_DEBUG("Detected %d harts.", dm->hart_count); LOG_TARGET_DEBUG(target, "Detected %d harts.", dm->hart_count);
} }
if (dm->hart_count == 0) { if (dm->hart_count == 0) {
LOG_ERROR("No harts found!"); LOG_TARGET_ERROR(target, "No harts found!");
return ERROR_FAIL; return ERROR_FAIL;
} }
@ -1962,10 +1962,10 @@ static int examine(struct target *target)
if (set_group(target, &info->haltgroup_supported, target->smp, HALT_GROUP) != ERROR_OK) if (set_group(target, &info->haltgroup_supported, target->smp, HALT_GROUP) != ERROR_OK)
return ERROR_FAIL; return ERROR_FAIL;
if (info->haltgroup_supported) if (info->haltgroup_supported)
LOG_INFO("Core %d made part of halt group %d.", target->coreid, LOG_TARGET_INFO(target, "Core %d made part of halt group %d.", target->coreid,
target->smp); target->smp);
else else
LOG_INFO("Core %d could not be made part of halt group %d.", LOG_TARGET_INFO(target, "Core %d could not be made part of halt group %d.",
target->coreid, target->smp); target->coreid, target->smp);
} }
@ -1981,7 +1981,7 @@ static int examine(struct target *target)
static int riscv013_authdata_read(struct target *target, uint32_t *value, unsigned int index) static int riscv013_authdata_read(struct target *target, uint32_t *value, unsigned int index)
{ {
if (index > 0) { if (index > 0) {
LOG_ERROR("Spec 0.13 only has a single authdata register."); LOG_TARGET_ERROR(target, "Spec 0.13 only has a single authdata register.");
return ERROR_FAIL; return ERROR_FAIL;
} }
@ -1994,7 +1994,7 @@ static int riscv013_authdata_read(struct target *target, uint32_t *value, unsign
static int riscv013_authdata_write(struct target *target, uint32_t value, unsigned int index) static int riscv013_authdata_write(struct target *target, uint32_t value, unsigned int index)
{ {
if (index > 0) { if (index > 0) {
LOG_ERROR("Spec 0.13 only has a single authdata register."); LOG_TARGET_ERROR(target, "Spec 0.13 only has a single authdata register.");
return ERROR_FAIL; return ERROR_FAIL;
} }
@ -2009,7 +2009,7 @@ static int riscv013_authdata_write(struct target *target, uint32_t value, unsign
if (!get_field(before, DM_DMSTATUS_AUTHENTICATED) && if (!get_field(before, DM_DMSTATUS_AUTHENTICATED) &&
get_field(after, DM_DMSTATUS_AUTHENTICATED)) { get_field(after, DM_DMSTATUS_AUTHENTICATED)) {
LOG_INFO("authdata_write resulted in successful authentication"); LOG_TARGET_INFO(target, "authdata_write resulted in successful authentication");
int result = ERROR_OK; int result = ERROR_OK;
dm013_info_t *dm = get_dm(target); dm013_info_t *dm = get_dm(target);
if (!dm) if (!dm)
@ -2064,7 +2064,7 @@ static unsigned riscv013_data_bits(struct target *target)
/* No further mem access method to try. */ /* No further mem access method to try. */
break; break;
} }
LOG_ERROR("Unable to determine supported data bits on this target. Assuming 32 bits."); LOG_TARGET_ERROR(target, "Unable to determine supported data bits on this target. Assuming 32 bits.");
return 32; return 32;
} }
@ -2346,12 +2346,12 @@ static int sample_memory_bus_v1(struct target *target,
RISCV013_INFO(info); RISCV013_INFO(info);
unsigned int sbasize = get_field(info->sbcs, DM_SBCS_SBASIZE); unsigned int sbasize = get_field(info->sbcs, DM_SBCS_SBASIZE);
if (sbasize > 64) { if (sbasize > 64) {
LOG_ERROR("Memory sampling is only implemented for sbasize <= 64."); LOG_TARGET_ERROR(target, "Memory sampling is only implemented for sbasize <= 64.");
return ERROR_NOT_IMPLEMENTED; return ERROR_NOT_IMPLEMENTED;
} }
if (get_field(info->sbcs, DM_SBCS_SBVERSION) != 1) { if (get_field(info->sbcs, DM_SBCS_SBVERSION) != 1) {
LOG_ERROR("Memory sampling is only implemented for SBA version 1."); LOG_TARGET_ERROR(target, "Memory sampling is only implemented for SBA version 1.");
return ERROR_NOT_IMPLEMENTED; return ERROR_NOT_IMPLEMENTED;
} }
@ -2389,7 +2389,7 @@ static int sample_memory_bus_v1(struct target *target,
for (unsigned int i = 0; i < ARRAY_SIZE(config->bucket); i++) { for (unsigned int i = 0; i < ARRAY_SIZE(config->bucket); i++) {
if (config->bucket[i].enabled) { if (config->bucket[i].enabled) {
if (!sba_supports_access(target, config->bucket[i].size_bytes)) { if (!sba_supports_access(target, config->bucket[i].size_bytes)) {
LOG_ERROR("Hardware does not support SBA access for %d-byte memory sampling.", LOG_TARGET_ERROR(target, "Hardware does not support SBA access for %d-byte memory sampling.",
config->bucket[i].size_bytes); config->bucket[i].size_bytes);
return ERROR_NOT_IMPLEMENTED; return ERROR_NOT_IMPLEMENTED;
} }
@ -2563,7 +2563,7 @@ static int tick(struct target *target)
static int init_target(struct command_context *cmd_ctx, static int init_target(struct command_context *cmd_ctx,
struct target *target) struct target *target)
{ {
LOG_DEBUG("init"); LOG_TARGET_DEBUG(target, "Init.");
RISCV_INFO(generic_info); RISCV_INFO(generic_info);
generic_info->get_register = &riscv013_get_register; generic_info->get_register = &riscv013_get_register;
@ -2839,7 +2839,7 @@ static int read_sbcs_nonbusy(struct target *target, uint32_t *sbcs)
if (!get_field(*sbcs, DM_SBCS_SBBUSY)) if (!get_field(*sbcs, DM_SBCS_SBBUSY))
return ERROR_OK; return ERROR_OK;
if (time(NULL) - start > riscv_command_timeout_sec) { if (time(NULL) - start > riscv_command_timeout_sec) {
LOG_ERROR("Timed out after %ds waiting for sbbusy to go low (sbcs=0x%x). " LOG_TARGET_ERROR(target, "Timed out after %ds waiting for sbbusy to go low (sbcs=0x%x). "
"Increase the timeout with riscv set_command_timeout_sec.", "Increase the timeout with riscv set_command_timeout_sec.",
riscv_command_timeout_sec, *sbcs); riscv_command_timeout_sec, *sbcs);
return ERROR_FAIL; return ERROR_FAIL;
@ -2882,11 +2882,11 @@ static int read_memory_bus_v0(struct target *target, target_addr_t address,
uint32_t size, uint32_t count, uint8_t *buffer, uint32_t increment) uint32_t size, uint32_t count, uint8_t *buffer, uint32_t increment)
{ {
if (size != increment) { if (size != increment) {
LOG_ERROR("sba v0 reads only support size==increment"); LOG_TARGET_ERROR(target, "sba v0 reads only support size==increment");
return ERROR_NOT_IMPLEMENTED; return ERROR_NOT_IMPLEMENTED;
} }
LOG_DEBUG("System Bus Access: size: %d\tcount:%d\tstart address: 0x%08" LOG_TARGET_DEBUG(target, "System Bus Access: size: %d\tcount:%d\tstart address: 0x%08"
TARGET_PRIxADDR, size, count, address); TARGET_PRIxADDR, size, count, address);
uint8_t *t_buffer = buffer; uint8_t *t_buffer = buffer;
riscv_addr_t cur_addr = address; riscv_addr_t cur_addr = address;
@ -2908,13 +2908,13 @@ static int read_memory_bus_v0(struct target *target, target_addr_t address,
/* size/2 matching the bit access of the spec 0.13 */ /* size/2 matching the bit access of the spec 0.13 */
access = set_field(access, DM_SBCS_SBACCESS, size/2); access = set_field(access, DM_SBCS_SBACCESS, size/2);
access = set_field(access, DM_SBCS_SBSINGLEREAD, 1); access = set_field(access, DM_SBCS_SBSINGLEREAD, 1);
LOG_DEBUG("\r\nread_memory: sab: access: 0x%08x", access); LOG_TARGET_DEBUG(target, "read_memory: sab: access: 0x%08x", access);
dmi_write(target, DM_SBCS, access); dmi_write(target, DM_SBCS, access);
/* 3) read */ /* 3) read */
uint32_t value; uint32_t value;
if (dmi_read(target, &value, DM_SBDATA0) != ERROR_OK) if (dmi_read(target, &value, DM_SBDATA0) != ERROR_OK)
return ERROR_FAIL; return ERROR_FAIL;
LOG_DEBUG("\r\nread_memory: sab: value: 0x%08x", value); LOG_TARGET_DEBUG(target, "read_memory: sab: value: 0x%08x", value);
buf_set_u32(t_buffer, 0, 8 * size, value); buf_set_u32(t_buffer, 0, 8 * size, value);
t_buffer += size; t_buffer += size;
cur_addr += size; cur_addr += size;
@ -2923,7 +2923,7 @@ static int read_memory_bus_v0(struct target *target, target_addr_t address,
} }
/* has to be the same size if we want to read a block */ /* has to be the same size if we want to read a block */
LOG_DEBUG("reading block until final address 0x%" PRIx64, fin_addr); LOG_TARGET_DEBUG(target, "Reading block until final address 0x%" PRIx64, fin_addr);
if (dmi_read(target, &access, DM_SBCS) != ERROR_OK) if (dmi_read(target, &access, DM_SBCS) != ERROR_OK)
return ERROR_FAIL; return ERROR_FAIL;
/* set current address */ /* set current address */
@ -2934,11 +2934,11 @@ static int read_memory_bus_v0(struct target *target, target_addr_t address,
access = set_field(access, DM_SBCS_SBAUTOREAD, 1); access = set_field(access, DM_SBCS_SBAUTOREAD, 1);
access = set_field(access, DM_SBCS_SBSINGLEREAD, 1); access = set_field(access, DM_SBCS_SBSINGLEREAD, 1);
access = set_field(access, DM_SBCS_SBAUTOINCREMENT, 1); access = set_field(access, DM_SBCS_SBAUTOINCREMENT, 1);
LOG_DEBUG("\r\naccess: 0x%08x", access); LOG_TARGET_DEBUG(target, "access: 0x%08x", access);
dmi_write(target, DM_SBCS, access); dmi_write(target, DM_SBCS, access);
while (cur_addr < fin_addr) { while (cur_addr < fin_addr) {
LOG_DEBUG("\r\nsab:autoincrement: \r\n size: %d\tcount:%d\taddress: 0x%08" LOG_TARGET_DEBUG(target, "sab:autoincrement:\r\n\tsize: %d\tcount:%d\taddress: 0x%08"
PRIx64, size, count, cur_addr); PRIx64, size, count, cur_addr);
/* read */ /* read */
uint32_t value; uint32_t value;
@ -2971,7 +2971,7 @@ static int read_memory_bus_v1(struct target *target, target_addr_t address,
uint32_t size, uint32_t count, uint8_t *buffer, uint32_t increment) uint32_t size, uint32_t count, uint8_t *buffer, uint32_t increment)
{ {
if (increment != size && increment != 0) { if (increment != size && increment != 0) {
LOG_ERROR("sba v1 reads only support increment of size or 0"); LOG_TARGET_ERROR(target, "sba v1 reads only support increment of size or 0");
return ERROR_NOT_IMPLEMENTED; return ERROR_NOT_IMPLEMENTED;
} }
@ -2996,7 +2996,7 @@ static int read_memory_bus_v1(struct target *target, target_addr_t address,
if (info->bus_master_read_delay) { if (info->bus_master_read_delay) {
jtag_add_runtest(info->bus_master_read_delay, TAP_IDLE); jtag_add_runtest(info->bus_master_read_delay, TAP_IDLE);
if (jtag_execute_queue() != ERROR_OK) { if (jtag_execute_queue() != ERROR_OK) {
LOG_ERROR("Failed to scan idle sequence"); LOG_TARGET_ERROR(target, "Failed to scan idle sequence");
return ERROR_FAIL; return ERROR_FAIL;
} }
} }
@ -3014,8 +3014,8 @@ static int read_memory_bus_v1(struct target *target, target_addr_t address,
unsigned attempt = 0; unsigned attempt = 0;
while (1) { while (1) {
if (attempt++ > 100) { if (attempt++ > 100) {
LOG_ERROR("DMI keeps being busy in while reading memory just past " TARGET_ADDR_FMT, LOG_TARGET_ERROR(target, "DMI keeps being busy in while reading memory"
next_read); " just past " TARGET_ADDR_FMT, next_read);
return ERROR_FAIL; return ERROR_FAIL;
} }
keep_alive(); keep_alive();
@ -3045,8 +3045,8 @@ static int read_memory_bus_v1(struct target *target, target_addr_t address,
unsigned attempt = 0; unsigned attempt = 0;
while (1) { while (1) {
if (attempt++ > 100) { if (attempt++ > 100) {
LOG_ERROR("DMI keeps being busy in while reading memory just past " TARGET_ADDR_FMT, LOG_TARGET_ERROR(target, "DMI keeps being busy in while reading memory"
next_read); " just past " TARGET_ADDR_FMT, next_read);
return ERROR_FAIL; return ERROR_FAIL;
} }
dmi_status_t status = dmi_scan(target, NULL, &sbvalue[0], DMI_OP_NOP, 0, 0, false); dmi_status_t status = dmi_scan(target, NULL, &sbvalue[0], DMI_OP_NOP, 0, 0, false);
@ -3135,9 +3135,9 @@ static void log_mem_access_result(struct target *target, bool success, int metho
} }
if (warn) if (warn)
LOG_WARNING("%s", msg); LOG_TARGET_WARNING(target, "%s", msg);
else else
LOG_DEBUG("%s", msg); LOG_TARGET_DEBUG(target, "%s", msg);
} }
static bool mem_should_skip_progbuf(struct target *target, target_addr_t address, static bool mem_should_skip_progbuf(struct target *target, target_addr_t address,
@ -3146,31 +3146,31 @@ static bool mem_should_skip_progbuf(struct target *target, target_addr_t address
assert(skip_reason); assert(skip_reason);
if (!has_sufficient_progbuf(target, 3)) { if (!has_sufficient_progbuf(target, 3)) {
LOG_DEBUG("Skipping mem %s via progbuf - insufficient progbuf size.", LOG_TARGET_DEBUG(target, "Skipping mem %s via progbuf - insufficient progbuf size.",
is_read ? "read" : "write"); is_read ? "read" : "write");
*skip_reason = "skipped (insufficient progbuf)"; *skip_reason = "skipped (insufficient progbuf)";
return true; return true;
} }
if (target->state != TARGET_HALTED) { if (target->state != TARGET_HALTED) {
LOG_DEBUG("Skipping mem %s via progbuf - target not halted.", LOG_TARGET_DEBUG(target, "Skipping mem %s via progbuf - target not halted.",
is_read ? "read" : "write"); is_read ? "read" : "write");
*skip_reason = "skipped (target not halted)"; *skip_reason = "skipped (target not halted)";
return true; return true;
} }
if (riscv_xlen(target) < size * 8) { if (riscv_xlen(target) < size * 8) {
LOG_DEBUG("Skipping mem %s via progbuf - XLEN (%d) is too short for %d-bit memory access.", LOG_TARGET_DEBUG(target, "Skipping mem %s via progbuf - XLEN (%d) is too short for %d-bit memory access.",
is_read ? "read" : "write", riscv_xlen(target), size * 8); is_read ? "read" : "write", riscv_xlen(target), size * 8);
*skip_reason = "skipped (XLEN too short)"; *skip_reason = "skipped (XLEN too short)";
return true; return true;
} }
if (size > 8) { if (size > 8) {
LOG_DEBUG("Skipping mem %s via progbuf - unsupported size.", LOG_TARGET_DEBUG(target, "Skipping mem %s via progbuf - unsupported size.",
is_read ? "read" : "write"); is_read ? "read" : "write");
*skip_reason = "skipped (unsupported size)"; *skip_reason = "skipped (unsupported size)";
return true; return true;
} }
if ((sizeof(address) * 8 > riscv_xlen(target)) && (address >> riscv_xlen(target))) { if ((sizeof(address) * 8 > riscv_xlen(target)) && (address >> riscv_xlen(target))) {
LOG_DEBUG("Skipping mem %s via progbuf - progbuf only supports %u-bit address.", LOG_TARGET_DEBUG(target, "Skipping mem %s via progbuf - progbuf only supports %u-bit address.",
is_read ? "read" : "write", riscv_xlen(target)); is_read ? "read" : "write", riscv_xlen(target));
*skip_reason = "skipped (too large address)"; *skip_reason = "skipped (too large address)";
return true; return true;
@ -3186,20 +3186,20 @@ static bool mem_should_skip_sysbus(struct target *target, target_addr_t address,
RISCV013_INFO(info); RISCV013_INFO(info);
if (!sba_supports_access(target, size)) { if (!sba_supports_access(target, size)) {
LOG_DEBUG("Skipping mem %s via system bus - unsupported size.", LOG_TARGET_DEBUG(target, "Skipping mem %s via system bus - unsupported size.",
is_read ? "read" : "write"); is_read ? "read" : "write");
*skip_reason = "skipped (unsupported size)"; *skip_reason = "skipped (unsupported size)";
return true; return true;
} }
unsigned int sbasize = get_field(info->sbcs, DM_SBCS_SBASIZE); unsigned int sbasize = get_field(info->sbcs, DM_SBCS_SBASIZE);
if ((sizeof(address) * 8 > sbasize) && (address >> sbasize)) { if ((sizeof(address) * 8 > sbasize) && (address >> sbasize)) {
LOG_DEBUG("Skipping mem %s via system bus - sba only supports %u-bit address.", LOG_TARGET_DEBUG(target, "Skipping mem %s via system bus - sba only supports %u-bit address.",
is_read ? "read" : "write", sbasize); is_read ? "read" : "write", sbasize);
*skip_reason = "skipped (too large address)"; *skip_reason = "skipped (too large address)";
return true; return true;
} }
if (is_read && increment != size && (get_field(info->sbcs, DM_SBCS_SBVERSION) == 0 || increment != 0)) { if (is_read && increment != size && (get_field(info->sbcs, DM_SBCS_SBVERSION) == 0 || increment != 0)) {
LOG_DEBUG("Skipping mem read via system bus - " LOG_TARGET_DEBUG(target, "Skipping mem read via system bus - "
"sba reads only support size==increment or also size==0 for sba v1."); "sba reads only support size==increment or also size==0 for sba v1.");
*skip_reason = "skipped (unsupported increment)"; *skip_reason = "skipped (unsupported increment)";
return true; return true;
@ -3216,19 +3216,19 @@ static bool mem_should_skip_abstract(struct target *target, target_addr_t addres
if (size > 8) { if (size > 8) {
/* TODO: Add 128b support if it's ever used. Involves modifying /* TODO: Add 128b support if it's ever used. Involves modifying
read/write_abstract_arg() to work on two 64b values. */ read/write_abstract_arg() to work on two 64b values. */
LOG_DEBUG("Skipping mem %s via abstract access - unsupported size: %d bits", LOG_TARGET_DEBUG(target, "Skipping mem %s via abstract access - unsupported size: %d bits",
is_read ? "read" : "write", size * 8); is_read ? "read" : "write", size * 8);
*skip_reason = "skipped (unsupported size)"; *skip_reason = "skipped (unsupported size)";
return true; return true;
} }
if ((sizeof(address) * 8 > riscv_xlen(target)) && (address >> riscv_xlen(target))) { if ((sizeof(address) * 8 > riscv_xlen(target)) && (address >> riscv_xlen(target))) {
LOG_DEBUG("Skipping mem %s via abstract access - abstract access only supports %u-bit address.", LOG_TARGET_DEBUG(target, "Skipping mem %s via abstract access - abstract access only supports %u-bit address.",
is_read ? "read" : "write", riscv_xlen(target)); is_read ? "read" : "write", riscv_xlen(target));
*skip_reason = "skipped (too large address)"; *skip_reason = "skipped (too large address)";
return true; return true;
} }
if (is_read && size != increment) { if (is_read && size != increment) {
LOG_ERROR("Skipping mem read via abstract access - " LOG_TARGET_ERROR(target, "Skipping mem read via abstract access - "
"abstract command reads only support size==increment."); "abstract command reads only support size==increment.");
*skip_reason = "skipped (unsupported increment)"; *skip_reason = "skipped (unsupported increment)";
return true; return true;
@ -3250,7 +3250,7 @@ static int read_memory_abstract(struct target *target, target_addr_t address,
int result = ERROR_OK; int result = ERROR_OK;
bool use_aampostincrement = info->has_aampostincrement != YNM_NO; bool use_aampostincrement = info->has_aampostincrement != YNM_NO;
LOG_DEBUG("reading %d words of %d bytes from 0x%" TARGET_PRIxADDR, count, LOG_TARGET_DEBUG(target, "Reading %d words of %d bytes from 0x%" TARGET_PRIxADDR, count,
size, address); size, address);
memset(buffer, 0, count * size); memset(buffer, 0, count * size);
@ -3271,7 +3271,7 @@ static int read_memory_abstract(struct target *target, target_addr_t address,
/* Set arg1 to the address: address + c * size */ /* Set arg1 to the address: address + c * size */
result = write_abstract_arg(target, 1, address + c * size, riscv_xlen(target)); result = write_abstract_arg(target, 1, address + c * size, riscv_xlen(target));
if (result != ERROR_OK) { if (result != ERROR_OK) {
LOG_ERROR("Failed to write arg1 during read_memory_abstract()."); LOG_TARGET_ERROR(target, "Failed to write arg1.");
return result; return result;
} }
} }
@ -3284,10 +3284,10 @@ static int read_memory_abstract(struct target *target, target_addr_t address,
/* Safety: double-check that the address was really auto-incremented */ /* Safety: double-check that the address was really auto-incremented */
riscv_reg_t new_address = read_abstract_arg(target, 1, riscv_xlen(target)); riscv_reg_t new_address = read_abstract_arg(target, 1, riscv_xlen(target));
if (new_address == address + size) { if (new_address == address + size) {
LOG_DEBUG("aampostincrement is supported on this target."); LOG_TARGET_DEBUG(target, "aampostincrement is supported on this target.");
info->has_aampostincrement = YNM_YES; info->has_aampostincrement = YNM_YES;
} else { } else {
LOG_WARNING("Buggy aampostincrement! Address not incremented correctly."); LOG_TARGET_WARNING(target, "Buggy aampostincrement! Address not incremented correctly.");
info->has_aampostincrement = YNM_NO; info->has_aampostincrement = YNM_NO;
} }
} else { } else {
@ -3295,7 +3295,7 @@ static int read_memory_abstract(struct target *target, target_addr_t address,
command = access_memory_command(target, false, width, false, false); command = access_memory_command(target, false, width, false, false);
result = execute_abstract_command(target, command); result = execute_abstract_command(target, command);
if (result == ERROR_OK) { if (result == ERROR_OK) {
LOG_DEBUG("aampostincrement is not supported on this target."); LOG_TARGET_DEBUG(target, "aampostincrement is not supported on this target.");
info->has_aampostincrement = YNM_NO; info->has_aampostincrement = YNM_NO;
} }
} }
@ -3328,7 +3328,7 @@ static int write_memory_abstract(struct target *target, target_addr_t address,
int result = ERROR_OK; int result = ERROR_OK;
bool use_aampostincrement = info->has_aampostincrement != YNM_NO; bool use_aampostincrement = info->has_aampostincrement != YNM_NO;
LOG_DEBUG("writing %d words of %d bytes from 0x%" TARGET_PRIxADDR, count, LOG_TARGET_DEBUG(target, "writing %d words of %d bytes from 0x%" TARGET_PRIxADDR, count,
size, address); size, address);
/* Convert the size (bytes) to width (bits) */ /* Convert the size (bytes) to width (bits) */
@ -3345,7 +3345,7 @@ static int write_memory_abstract(struct target *target, target_addr_t address,
riscv_reg_t value = buf_get_u64(p, 0, 8 * size); riscv_reg_t value = buf_get_u64(p, 0, 8 * size);
result = write_abstract_arg(target, 0, value, riscv_xlen(target)); result = write_abstract_arg(target, 0, value, riscv_xlen(target));
if (result != ERROR_OK) { if (result != ERROR_OK) {
LOG_ERROR("Failed to write arg0 during write_memory_abstract()."); LOG_TARGET_ERROR(target, "Failed to write arg0.");
return result; return result;
} }
@ -3354,7 +3354,7 @@ static int write_memory_abstract(struct target *target, target_addr_t address,
/* Set arg1 to the address: address + c * size */ /* Set arg1 to the address: address + c * size */
result = write_abstract_arg(target, 1, address + c * size, riscv_xlen(target)); result = write_abstract_arg(target, 1, address + c * size, riscv_xlen(target));
if (result != ERROR_OK) { if (result != ERROR_OK) {
LOG_ERROR("Failed to write arg1 during write_memory_abstract()."); LOG_TARGET_ERROR(target, "Failed to write arg1.");
return result; return result;
} }
} }
@ -3367,10 +3367,10 @@ static int write_memory_abstract(struct target *target, target_addr_t address,
/* Safety: double-check that the address was really auto-incremented */ /* Safety: double-check that the address was really auto-incremented */
riscv_reg_t new_address = read_abstract_arg(target, 1, riscv_xlen(target)); riscv_reg_t new_address = read_abstract_arg(target, 1, riscv_xlen(target));
if (new_address == address + size) { if (new_address == address + size) {
LOG_DEBUG("aampostincrement is supported on this target."); LOG_TARGET_DEBUG(target, "aampostincrement is supported on this target.");
info->has_aampostincrement = YNM_YES; info->has_aampostincrement = YNM_YES;
} else { } else {
LOG_WARNING("Buggy aampostincrement! Address not incremented correctly."); LOG_TARGET_WARNING(target, "Buggy aampostincrement! Address not incremented correctly.");
info->has_aampostincrement = YNM_NO; info->has_aampostincrement = YNM_NO;
} }
} else { } else {
@ -3378,7 +3378,7 @@ static int write_memory_abstract(struct target *target, target_addr_t address,
command = access_memory_command(target, false, width, false, true); command = access_memory_command(target, false, width, false, true);
result = execute_abstract_command(target, command); result = execute_abstract_command(target, command);
if (result == ERROR_OK) { if (result == ERROR_OK) {
LOG_DEBUG("aampostincrement is not supported on this target."); LOG_TARGET_DEBUG(target, "aampostincrement is not supported on this target.");
info->has_aampostincrement = YNM_NO; info->has_aampostincrement = YNM_NO;
} }
} }
@ -3961,7 +3961,7 @@ static int read_memory(struct target *target, target_addr_t address,
return ERROR_OK; return ERROR_OK;
if (size != 1 && size != 2 && size != 4 && size != 8 && size != 16) { if (size != 1 && size != 2 && size != 4 && size != 8 && size != 16) {
LOG_ERROR("BUG: Unsupported size for memory read: %d", size); LOG_TARGET_ERROR(target, "BUG: Unsupported size for memory read: %d", size);
return ERROR_FAIL; return ERROR_FAIL;
} }
@ -4013,8 +4013,8 @@ static int read_memory(struct target *target, target_addr_t address,
return ret; return ret;
} }
LOG_ERROR("Target %s: Failed to read memory (addr=0x%" PRIx64 ")", target_name(target), address); LOG_TARGET_ERROR(target, "Failed to read memory (addr=0x%" PRIx64 ")", address);
LOG_ERROR(" progbuf=%s, sysbus=%s, abstract=%s", progbuf_result, sysbus_result, abstract_result); LOG_TARGET_ERROR(target, " progbuf=%s, sysbus=%s, abstract=%s", progbuf_result, sysbus_result, abstract_result);
return ret; return ret;
} }
@ -4022,7 +4022,7 @@ static int write_memory_bus_v0(struct target *target, target_addr_t address,
uint32_t size, uint32_t count, const uint8_t *buffer) uint32_t size, uint32_t count, const uint8_t *buffer)
{ {
/*1) write sbaddress: for singlewrite and autoincrement, we need to write the address once*/ /*1) write sbaddress: for singlewrite and autoincrement, we need to write the address once*/
LOG_DEBUG("System Bus Access: size: %d\tcount:%d\tstart address: 0x%08" LOG_TARGET_DEBUG(target, "System Bus Access: size: %d\tcount:%d\tstart address: 0x%08"
TARGET_PRIxADDR, size, count, address); TARGET_PRIxADDR, size, count, address);
dmi_write(target, DM_SBADDRESS0, address); dmi_write(target, DM_SBADDRESS0, address);
int64_t value = 0; int64_t value = 0;
@ -4038,8 +4038,8 @@ static int write_memory_bus_v0(struct target *target, target_addr_t address,
access = 0; access = 0;
access = set_field(access, DM_SBCS_SBACCESS, size/2); access = set_field(access, DM_SBCS_SBACCESS, size/2);
dmi_write(target, DM_SBCS, access); dmi_write(target, DM_SBCS, access);
LOG_DEBUG("\r\naccess: 0x%08" PRIx64, access); LOG_TARGET_DEBUG(target, " access: 0x%08" PRIx64, access);
LOG_DEBUG("\r\nwrite_memory:SAB: ONE OFF: value 0x%08" PRIx64, value); LOG_TARGET_DEBUG(target, " write_memory:SAB: ONE OFF: value 0x%08" PRIx64, value);
dmi_write(target, DM_SBDATA0, value); dmi_write(target, DM_SBDATA0, value);
return ERROR_OK; return ERROR_OK;
} }
@ -4049,7 +4049,7 @@ static int write_memory_bus_v0(struct target *target, target_addr_t address,
access = 0; access = 0;
access = set_field(access, DM_SBCS_SBACCESS, size/2); access = set_field(access, DM_SBCS_SBACCESS, size/2);
access = set_field(access, DM_SBCS_SBAUTOINCREMENT, 1); access = set_field(access, DM_SBCS_SBAUTOINCREMENT, 1);
LOG_DEBUG("\r\naccess: 0x%08" PRIx64, access); LOG_TARGET_DEBUG(target, " access: 0x%08" PRIx64, access);
dmi_write(target, DM_SBCS, access); dmi_write(target, DM_SBCS, access);
/*2)set the value according to the size required and write*/ /*2)set the value according to the size required and write*/
@ -4060,7 +4060,7 @@ static int write_memory_bus_v0(struct target *target, target_addr_t address,
t_buffer = buffer + offset; t_buffer = buffer + offset;
value = buf_get_u64(t_buffer, 0, 8 * size); value = buf_get_u64(t_buffer, 0, 8 * size);
LOG_DEBUG("SAB:autoincrement: expected address: 0x%08x value: 0x%08x" LOG_TARGET_DEBUG(target, "SAB:autoincrement: expected address: 0x%08x value: 0x%08x"
PRIx64, (uint32_t)t_addr, (uint32_t)value); PRIx64, (uint32_t)t_addr, (uint32_t)value);
dmi_write(target, DM_SBDATA0, value); dmi_write(target, DM_SBDATA0, value);
} }
@ -4086,7 +4086,7 @@ static int write_memory_bus_v1(struct target *target, target_addr_t address,
sb_write_address(target, next_address, true); sb_write_address(target, next_address, true);
while (next_address < end_address) { while (next_address < end_address) {
LOG_DEBUG("transferring burst starting at address 0x%" TARGET_PRIxADDR, LOG_TARGET_DEBUG(target, "Transferring burst starting at address 0x%" TARGET_PRIxADDR,
next_address); next_address);
struct riscv_batch *batch = riscv_batch_alloc( struct riscv_batch *batch = riscv_batch_alloc(
@ -4154,13 +4154,13 @@ static int write_memory_bus_v1(struct target *target, target_addr_t address,
DM_SBCS, 0, false, true) != ERROR_OK) DM_SBCS, 0, false, true) != ERROR_OK)
return ERROR_FAIL; return ERROR_FAIL;
if (dmi_busy_encountered) if (dmi_busy_encountered)
LOG_DEBUG("DMI busy encountered during system bus write."); LOG_TARGET_DEBUG(target, "DMI busy encountered during system bus write.");
/* Wait until sbbusy goes low */ /* Wait until sbbusy goes low */
time_t start = time(NULL); time_t start = time(NULL);
while (get_field(sbcs, DM_SBCS_SBBUSY)) { while (get_field(sbcs, DM_SBCS_SBBUSY)) {
if (time(NULL) - start > riscv_command_timeout_sec) { if (time(NULL) - start > riscv_command_timeout_sec) {
LOG_ERROR("Timed out after %ds waiting for sbbusy to go low (sbcs=0x%x). " LOG_TARGET_ERROR(target, "Timed out after %ds waiting for sbbusy to go low (sbcs=0x%x). "
"Increase the timeout with riscv set_command_timeout_sec.", "Increase the timeout with riscv set_command_timeout_sec.",
riscv_command_timeout_sec, sbcs); riscv_command_timeout_sec, sbcs);
return ERROR_FAIL; return ERROR_FAIL;
@ -4171,7 +4171,7 @@ static int write_memory_bus_v1(struct target *target, target_addr_t address,
if (get_field(sbcs, DM_SBCS_SBBUSYERROR)) { if (get_field(sbcs, DM_SBCS_SBBUSYERROR)) {
/* We wrote while the target was busy. */ /* We wrote while the target was busy. */
LOG_DEBUG("Sbbusyerror encountered during system bus write."); LOG_TARGET_DEBUG(target, "Sbbusyerror encountered during system bus write.");
/* Clear the sticky error flag. */ /* Clear the sticky error flag. */
dmi_write(target, DM_SBCS, sbcs | DM_SBCS_SBBUSYERROR); dmi_write(target, DM_SBCS, sbcs | DM_SBCS_SBBUSYERROR);
/* Slow down before trying again. */ /* Slow down before trying again. */
@ -4184,7 +4184,7 @@ static int write_memory_bus_v1(struct target *target, target_addr_t address,
next_address = sb_read_address(target); next_address = sb_read_address(target);
if (next_address < address) { if (next_address < address) {
/* This should never happen, probably buggy hardware. */ /* This should never happen, probably buggy hardware. */
LOG_DEBUG("unexpected sbaddress=0x%" TARGET_PRIxADDR LOG_TARGET_DEBUG(target, "unexpected sbaddress=0x%" TARGET_PRIxADDR
" - buggy sbautoincrement in hw?", next_address); " - buggy sbautoincrement in hw?", next_address);
/* Fail the whole operation. */ /* Fail the whole operation. */
return ERROR_FAIL; return ERROR_FAIL;
@ -4200,12 +4200,12 @@ static int write_memory_bus_v1(struct target *target, target_addr_t address,
* (unless sbautoincrement in the HW is buggy). * (unless sbautoincrement in the HW is buggy).
*/ */
target_addr_t sbaddress = sb_read_address(target); target_addr_t sbaddress = sb_read_address(target);
LOG_DEBUG("System bus access failed with sberror=%u (sbaddress=0x%" TARGET_PRIxADDR ")", LOG_TARGET_DEBUG(target, "System bus access failed with sberror=%u (sbaddress=0x%" TARGET_PRIxADDR ")",
sberror, sbaddress); sberror, sbaddress);
if (sbaddress < address) { if (sbaddress < address) {
/* This should never happen, probably buggy hardware. /* This should never happen, probably buggy hardware.
* Make a note to the user not to trust the sbaddress value. */ * Make a note to the user not to trust the sbaddress value. */
LOG_DEBUG("unexpected sbaddress=0x%" TARGET_PRIxADDR LOG_TARGET_DEBUG(target, "unexpected sbaddress=0x%" TARGET_PRIxADDR
" - buggy sbautoincrement in hw?", next_address); " - buggy sbautoincrement in hw?", next_address);
} }
/* Clear the sticky error flag */ /* Clear the sticky error flag */
@ -4224,12 +4224,12 @@ static int write_memory_progbuf(struct target *target, target_addr_t address,
RISCV013_INFO(info); RISCV013_INFO(info);
if (riscv_xlen(target) < size * 8) { if (riscv_xlen(target) < size * 8) {
LOG_ERROR("XLEN (%d) is too short for %d-bit memory write.", LOG_TARGET_ERROR(target, "XLEN (%d) is too short for %d-bit memory write.",
riscv_xlen(target), size * 8); riscv_xlen(target), size * 8);
return ERROR_FAIL; return ERROR_FAIL;
} }
LOG_DEBUG("writing %d words of %d bytes to 0x%08lx", count, size, (long)address); LOG_TARGET_DEBUG(target, "writing %d words of %d bytes to 0x%08lx", count, size, (long)address);
select_dmi(target); select_dmi(target);
@ -4268,7 +4268,7 @@ static int write_memory_progbuf(struct target *target, target_addr_t address,
riscv_program_sdr(&program, GDB_REGNO_S1, GDB_REGNO_S0, 0); riscv_program_sdr(&program, GDB_REGNO_S1, GDB_REGNO_S0, 0);
break; break;
default: default:
LOG_ERROR("write_memory_progbuf(): Unsupported size: %d", size); LOG_TARGET_ERROR(target, "Unsupported size: %d", size);
result = ERROR_FAIL; result = ERROR_FAIL;
goto error; goto error;
} }
@ -4285,9 +4285,9 @@ static int write_memory_progbuf(struct target *target, target_addr_t address,
riscv_addr_t cur_addr = address; riscv_addr_t cur_addr = address;
riscv_addr_t distance = (riscv_addr_t)count * size; riscv_addr_t distance = (riscv_addr_t)count * size;
bool setup_needed = true; bool setup_needed = true;
LOG_DEBUG("writing until final address 0x%016" PRIx64, cur_addr + distance); LOG_TARGET_DEBUG(target, "Writing until final address 0x%016" PRIx64, cur_addr + distance);
while (cur_addr - address < distance) { while (cur_addr - address < distance) {
LOG_DEBUG("transferring burst starting at address 0x%016" PRIx64, LOG_TARGET_DEBUG(target, "Transferring burst starting at address 0x%016" PRIx64,
cur_addr); cur_addr);
struct riscv_batch *batch = riscv_batch_alloc( struct riscv_batch *batch = riscv_batch_alloc(
@ -4370,12 +4370,12 @@ static int write_memory_progbuf(struct target *target, target_addr_t address,
return ERROR_FAIL; return ERROR_FAIL;
info->cmderr = get_field(abstractcs, DM_ABSTRACTCS_CMDERR); info->cmderr = get_field(abstractcs, DM_ABSTRACTCS_CMDERR);
if (info->cmderr == CMDERR_NONE && !dmi_busy_encountered) { if (info->cmderr == CMDERR_NONE && !dmi_busy_encountered) {
LOG_DEBUG("successful (partial?) memory write"); LOG_TARGET_DEBUG(target, "Successful (partial?) memory write");
} else if (info->cmderr == CMDERR_BUSY || dmi_busy_encountered) { } else if (info->cmderr == CMDERR_BUSY || dmi_busy_encountered) {
if (info->cmderr == CMDERR_BUSY) if (info->cmderr == CMDERR_BUSY)
LOG_DEBUG("Memory write resulted in abstract command busy response."); LOG_TARGET_DEBUG(target, "Memory write resulted in abstract command busy response.");
else if (dmi_busy_encountered) else if (dmi_busy_encountered)
LOG_DEBUG("Memory write resulted in DMI busy response."); LOG_TARGET_DEBUG(target, "Memory write resulted in DMI busy response.");
riscv013_clear_abstract_error(target); riscv013_clear_abstract_error(target);
increase_ac_busy_delay(target); increase_ac_busy_delay(target);
@ -4385,7 +4385,7 @@ static int write_memory_progbuf(struct target *target, target_addr_t address,
goto error; goto error;
setup_needed = true; setup_needed = true;
} else { } else {
LOG_ERROR("error when writing memory, abstractcs=0x%08lx", (long)abstractcs); LOG_TARGET_ERROR(target, "Error when writing memory, abstractcs=0x%08lx", (long)abstractcs);
riscv013_clear_abstract_error(target); riscv013_clear_abstract_error(target);
result = ERROR_FAIL; result = ERROR_FAIL;
goto error; goto error;
@ -4410,7 +4410,7 @@ static int write_memory(struct target *target, target_addr_t address,
uint32_t size, uint32_t count, const uint8_t *buffer) uint32_t size, uint32_t count, const uint8_t *buffer)
{ {
if (size != 1 && size != 2 && size != 4 && size != 8 && size != 16) { if (size != 1 && size != 2 && size != 4 && size != 8 && size != 16) {
LOG_ERROR("BUG: Unsupported size for memory write: %d", size); LOG_TARGET_ERROR(target, "BUG: Unsupported size for memory write: %d", size);
return ERROR_FAIL; return ERROR_FAIL;
} }
@ -4462,8 +4462,8 @@ static int write_memory(struct target *target, target_addr_t address,
return ret; return ret;
} }
LOG_ERROR("Target %s: Failed to write memory (addr=0x%" PRIx64 ")", target_name(target), address); LOG_TARGET_ERROR(target, "Target %s: Failed to write memory (addr=0x%" PRIx64 ")", target_name(target), address);
LOG_ERROR(" progbuf=%s, sysbus=%s, abstract=%s", progbuf_result, sysbus_result, abstract_result); LOG_TARGET_ERROR(target, " progbuf=%s, sysbus=%s, abstract=%s", progbuf_result, sysbus_result, abstract_result);
return ret; return ret;
} }
@ -4596,7 +4596,7 @@ static int select_prepped_harts(struct target *target)
struct riscv_info *info = riscv_info(t); struct riscv_info *info = riscv_info(t);
riscv013_info_t *info_013 = get_info(t); riscv013_info_t *info_013 = get_info(t);
unsigned int index = info_013->index; unsigned int index = info_013->index;
LOG_DEBUG("index=%d, coreid=%d, prepped=%d", index, t->coreid, info->prepped); LOG_TARGET_DEBUG(target, "index=%d, coreid=%d, prepped=%d", index, t->coreid, info->prepped);
if (info->prepped) { if (info->prepped) {
info_013->selected = true; info_013->selected = true;
hawindow[index / 32] |= 1 << (index % 32); hawindow[index / 32] |= 1 << (index % 32);
@ -4767,7 +4767,7 @@ static enum riscv_halt_reason riscv013_halt_reason(struct target *target)
* already set when we connected. Force enumeration now, which has the * already set when we connected. Force enumeration now, which has the
* side effect of clearing any triggers we did not set. */ * side effect of clearing any triggers we did not set. */
riscv_enumerate_triggers(target); riscv_enumerate_triggers(target);
LOG_DEBUG("{%d} halted because of trigger", target->coreid); LOG_TARGET_DEBUG(target, "Coreid: [%d] halted because of trigger", target->coreid);
return RISCV_HALT_TRIGGER; return RISCV_HALT_TRIGGER;
case CSR_DCSR_CAUSE_STEP: case CSR_DCSR_CAUSE_STEP:
return RISCV_HALT_SINGLESTEP; return RISCV_HALT_SINGLESTEP;
@ -4778,8 +4778,8 @@ static enum riscv_halt_reason riscv013_halt_reason(struct target *target)
return RISCV_HALT_GROUP; return RISCV_HALT_GROUP;
} }
LOG_ERROR("Unknown DCSR cause field: 0x%" PRIx64, get_field(dcsr, CSR_DCSR_CAUSE)); LOG_TARGET_ERROR(target, "Unknown DCSR cause field: 0x%" PRIx64, get_field(dcsr, CSR_DCSR_CAUSE));
LOG_ERROR(" dcsr=0x%" PRIx32, (uint32_t)dcsr); LOG_TARGET_ERROR(target, " dcsr=0x%" PRIx32, (uint32_t)dcsr);
return RISCV_HALT_UNKNOWN; return RISCV_HALT_UNKNOWN;
} }
@ -4793,7 +4793,7 @@ static int riscv013_write_debug_buffer(struct target *target, unsigned int index
return ERROR_FAIL; return ERROR_FAIL;
dm->progbuf_cache[index] = data; dm->progbuf_cache[index] = data;
} else { } else {
LOG_DEBUG("cache hit for 0x%" PRIx32 " @%d", data, index); LOG_TARGET_DEBUG(target, "Cache hit for 0x%" PRIx32 " @%d", data, index);
} }
return ERROR_OK; return ERROR_OK;
} }
@ -4925,7 +4925,7 @@ static int riscv013_step_or_resume_current_hart(struct target *target,
LOG_TARGET_ERROR(target, " dmstatus=0x%08x", dmstatus); LOG_TARGET_ERROR(target, " dmstatus=0x%08x", dmstatus);
if (step) { if (step) {
LOG_ERROR(" was stepping, halting"); LOG_TARGET_ERROR(target, " was stepping, halting");
riscv_halt(target); riscv_halt(target);
return ERROR_OK; return ERROR_OK;
} }
@ -4943,7 +4943,7 @@ static void riscv013_clear_abstract_error(struct target *target)
dmi_read(target, &abstractcs, DM_ABSTRACTCS); dmi_read(target, &abstractcs, DM_ABSTRACTCS);
if (time(NULL) - start > riscv_command_timeout_sec) { if (time(NULL) - start > riscv_command_timeout_sec) {
LOG_ERROR("abstractcs.busy is not going low after %d seconds " LOG_TARGET_ERROR(target, "abstractcs.busy is not going low after %d seconds "
"(abstractcs=0x%x). The target is either really slow or " "(abstractcs=0x%x). The target is either really slow or "
"broken. You could increase the timeout with riscv " "broken. You could increase the timeout with riscv "
"set_command_timeout_sec.", "set_command_timeout_sec.",

261
src/target/riscv/riscv.c
View File

@ -379,7 +379,7 @@ static uint32_t dtmcontrol_scan(struct target *target, uint32_t out)
static struct target_type *get_target_type(struct target *target) static struct target_type *get_target_type(struct target *target)
{ {
if (!target->arch_info) { if (!target->arch_info) {
LOG_ERROR("Target has not been initialized"); LOG_TARGET_ERROR(target, "Target has not been initialized.");
return NULL; return NULL;
} }
@ -390,18 +390,18 @@ static struct target_type *get_target_type(struct target *target)
case 1: case 1:
return &riscv013_target; return &riscv013_target;
default: default:
LOG_ERROR("[%s] Unsupported DTM version: %d", LOG_TARGET_ERROR(target, "Unsupported DTM version: %d",
target_name(target), info->dtm_version); info->dtm_version);
return NULL; return NULL;
} }
} }
static int riscv_create_target(struct target *target, Jim_Interp *interp) static int riscv_create_target(struct target *target, Jim_Interp *interp)
{ {
LOG_DEBUG("riscv_create_target()"); LOG_TARGET_DEBUG(target, "riscv_create_target()");
target->arch_info = calloc(1, sizeof(struct riscv_info)); target->arch_info = calloc(1, sizeof(struct riscv_info));
if (!target->arch_info) { if (!target->arch_info) {
LOG_ERROR("Failed to allocate RISC-V target structure."); LOG_TARGET_ERROR(target, "Failed to allocate RISC-V target structure.");
return ERROR_FAIL; return ERROR_FAIL;
} }
riscv_info_init(target, target->arch_info); riscv_info_init(target, target->arch_info);
@ -411,7 +411,7 @@ static int riscv_create_target(struct target *target, Jim_Interp *interp)
static int riscv_init_target(struct command_context *cmd_ctx, static int riscv_init_target(struct command_context *cmd_ctx,
struct target *target) struct target *target)
{ {
LOG_DEBUG("riscv_init_target()"); LOG_TARGET_DEBUG(target, "riscv_init_target()");
RISCV_INFO(info); RISCV_INFO(info);
info->cmd_ctx = cmd_ctx; info->cmd_ctx = cmd_ctx;
@ -461,13 +461,13 @@ static void riscv_free_registers(struct target *target)
static void riscv_deinit_target(struct target *target) static void riscv_deinit_target(struct target *target)
{ {
LOG_DEBUG("riscv_deinit_target()"); LOG_TARGET_DEBUG(target, "riscv_deinit_target()");
struct riscv_info *info = target->arch_info; struct riscv_info *info = target->arch_info;
struct target_type *tt = get_target_type(target); struct target_type *tt = get_target_type(target);
if (riscv_flush_registers(target) != ERROR_OK) if (riscv_flush_registers(target) != ERROR_OK)
LOG_ERROR("[%s] Failed to flush registers. Ignoring this error.", target_name(target)); LOG_TARGET_ERROR(target, "Failed to flush registers. Ignoring this error.");
if (tt && info && info->version_specific) if (tt && info && info->version_specific)
tt->deinit_target(target); tt->deinit_target(target);
@ -1172,19 +1172,20 @@ static int riscv_add_breakpoint(struct target *target, struct breakpoint *breakp
if (breakpoint->type == BKPT_SOFT) { if (breakpoint->type == BKPT_SOFT) {
/** @todo check RVC for size/alignment */ /** @todo check RVC for size/alignment */
if (!(breakpoint->length == 4 || breakpoint->length == 2)) { if (!(breakpoint->length == 4 || breakpoint->length == 2)) {
LOG_ERROR("Invalid breakpoint length %d", breakpoint->length); LOG_TARGET_ERROR(target, "Invalid breakpoint length %d", breakpoint->length);
return ERROR_FAIL; return ERROR_FAIL;
} }
if (0 != (breakpoint->address % 2)) { if (0 != (breakpoint->address % 2)) {
LOG_ERROR("Invalid breakpoint alignment for address 0x%" TARGET_PRIxADDR, breakpoint->address); LOG_TARGET_ERROR(target, "Invalid breakpoint alignment for address 0x%" TARGET_PRIxADDR,
breakpoint->address);
return ERROR_FAIL; return ERROR_FAIL;
} }
/* Read the original instruction. */ /* Read the original instruction. */
if (riscv_read_by_any_size( if (riscv_read_by_any_size(
target, breakpoint->address, breakpoint->length, breakpoint->orig_instr) != ERROR_OK) { target, breakpoint->address, breakpoint->length, breakpoint->orig_instr) != ERROR_OK) {
LOG_ERROR("Failed to read original instruction at 0x%" TARGET_PRIxADDR, LOG_TARGET_ERROR(target, "Failed to read original instruction at 0x%" TARGET_PRIxADDR,
breakpoint->address); breakpoint->address);
return ERROR_FAIL; return ERROR_FAIL;
} }
@ -1193,7 +1194,7 @@ static int riscv_add_breakpoint(struct target *target, struct breakpoint *breakp
buf_set_u32(buff, 0, breakpoint->length * CHAR_BIT, breakpoint->length == 4 ? ebreak() : ebreak_c()); buf_set_u32(buff, 0, breakpoint->length * CHAR_BIT, breakpoint->length == 4 ? ebreak() : ebreak_c());
/* Write the ebreak instruction. */ /* Write the ebreak instruction. */
if (riscv_write_by_any_size(target, breakpoint->address, breakpoint->length, buff) != ERROR_OK) { if (riscv_write_by_any_size(target, breakpoint->address, breakpoint->length, buff) != ERROR_OK) {
LOG_ERROR("Failed to write %d-byte breakpoint instruction at 0x%" LOG_TARGET_ERROR(target, "Failed to write %d-byte breakpoint instruction at 0x%"
TARGET_PRIxADDR, breakpoint->length, breakpoint->address); TARGET_PRIxADDR, breakpoint->length, breakpoint->address);
return ERROR_FAIL; return ERROR_FAIL;
} }
@ -1205,7 +1206,7 @@ static int riscv_add_breakpoint(struct target *target, struct breakpoint *breakp
if (result != ERROR_OK) if (result != ERROR_OK)
return result; return result;
} else { } else {
LOG_INFO("OpenOCD only supports hardware and software breakpoints."); LOG_TARGET_INFO(target, "OpenOCD only supports hardware and software breakpoints.");
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
} }
@ -1237,8 +1238,8 @@ static int remove_trigger(struct target *target, int unique_id)
} }
} }
if (!done) { if (!done) {
LOG_ERROR("Couldn't find the hardware resources used by hardware " LOG_TARGET_ERROR(target,
"trigger."); "Couldn't find the hardware resources used by hardware trigger.");
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
} }
@ -1254,7 +1255,7 @@ static int riscv_remove_breakpoint(struct target *target,
/* Write the original instruction. */ /* Write the original instruction. */
if (riscv_write_by_any_size( if (riscv_write_by_any_size(
target, breakpoint->address, breakpoint->length, breakpoint->orig_instr) != ERROR_OK) { target, breakpoint->address, breakpoint->length, breakpoint->orig_instr) != ERROR_OK) {
LOG_ERROR("Failed to restore instruction for %d-byte breakpoint at " LOG_TARGET_ERROR(target, "Failed to restore instruction for %d-byte breakpoint at "
"0x%" TARGET_PRIxADDR, breakpoint->length, breakpoint->address); "0x%" TARGET_PRIxADDR, breakpoint->length, breakpoint->address);
return ERROR_FAIL; return ERROR_FAIL;
} }
@ -1267,7 +1268,7 @@ static int riscv_remove_breakpoint(struct target *target,
return result; return result;
} else { } else {
LOG_INFO("OpenOCD only supports hardware and software breakpoints."); LOG_TARGET_INFO(target, "OpenOCD only supports hardware and software breakpoints.");
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
} }
@ -1306,7 +1307,7 @@ int riscv_add_watchpoint(struct target *target, struct watchpoint *watchpoint)
int riscv_remove_watchpoint(struct target *target, int riscv_remove_watchpoint(struct target *target,
struct watchpoint *watchpoint) struct watchpoint *watchpoint)
{ {
LOG_DEBUG("[%d] @0x%" TARGET_PRIxADDR, target->coreid, watchpoint->address); LOG_TARGET_DEBUG(target, "Removing watchpoint @0x%" TARGET_PRIxADDR, watchpoint->address);
struct trigger trigger; struct trigger trigger;
trigger_from_watchpoint(&trigger, watchpoint); trigger_from_watchpoint(&trigger, watchpoint);
@ -1366,7 +1367,7 @@ static int riscv_hit_trigger_hit_bit(struct target *target, uint32_t *unique_id)
hit_mask = CSR_ETRIGGER_HIT(riscv_xlen(target)); hit_mask = CSR_ETRIGGER_HIT(riscv_xlen(target));
break; break;
default: default:
LOG_DEBUG("trigger %d has unknown type %d", i, type); LOG_TARGET_DEBUG(target, "Trigger %d has unknown type %d", i, type);
continue; continue;
} }
@ -1374,7 +1375,7 @@ static int riscv_hit_trigger_hit_bit(struct target *target, uint32_t *unique_id)
* to be changed to ignore triggers that are not the last one in * to be changed to ignore triggers that are not the last one in
* the chain. */ * the chain. */
if (tdata1 & hit_mask) { if (tdata1 & hit_mask) {
LOG_DEBUG("Trigger %d (unique_id=%d) has hit bit set.", i, r->trigger_unique_id[i]); LOG_TARGET_DEBUG(target, "Trigger %d (unique_id=%d) has hit bit set.", i, r->trigger_unique_id[i]);
if (riscv_set_register(target, GDB_REGNO_TDATA1, tdata1 & ~hit_mask) != ERROR_OK) if (riscv_set_register(target, GDB_REGNO_TDATA1, tdata1 & ~hit_mask) != ERROR_OK)
return ERROR_FAIL; return ERROR_FAIL;
@ -1413,22 +1414,22 @@ static int riscv_hit_watchpoint(struct target *target, struct watchpoint **hit_w
riscv_reg_t dpc; riscv_reg_t dpc;
riscv_get_register(target, &dpc, GDB_REGNO_DPC); riscv_get_register(target, &dpc, GDB_REGNO_DPC);
const uint8_t length = 4; const uint8_t length = 4;
LOG_DEBUG("dpc is 0x%" PRIx64, dpc); LOG_TARGET_DEBUG(target, "dpc is 0x%" PRIx64, dpc);
/* fetch the instruction at dpc */ /* fetch the instruction at dpc */
uint8_t buffer[length]; uint8_t buffer[length];
if (target_read_buffer(target, dpc, length, buffer) != ERROR_OK) { if (target_read_buffer(target, dpc, length, buffer) != ERROR_OK) {
LOG_ERROR("Failed to read instruction at dpc 0x%" PRIx64, dpc); LOG_TARGET_ERROR(target, "Failed to read instruction at dpc 0x%" PRIx64, dpc);
return ERROR_FAIL; return ERROR_FAIL;
} }
uint32_t instruction = 0; uint32_t instruction = 0;
for (int i = 0; i < length; i++) { for (int i = 0; i < length; i++) {
LOG_DEBUG("Next byte is %x", buffer[i]); LOG_TARGET_DEBUG(target, "Next byte is %x", buffer[i]);
instruction += (buffer[i] << 8 * i); instruction += (buffer[i] << 8 * i);
} }
LOG_DEBUG("Full instruction is %x", instruction); LOG_TARGET_DEBUG(target, "Full instruction is %x", instruction);
/* find out which memory address is accessed by the instruction at dpc */ /* find out which memory address is accessed by the instruction at dpc */
/* opcode is first 7 bits of the instruction */ /* opcode is first 7 bits of the instruction */
@ -1442,19 +1443,19 @@ static int riscv_hit_watchpoint(struct target *target, struct watchpoint **hit_w
riscv_get_register(target, &mem_addr, rs1); riscv_get_register(target, &mem_addr, rs1);
if (opcode == MATCH_SB) { if (opcode == MATCH_SB) {
LOG_DEBUG("%x is store instruction", instruction); LOG_TARGET_DEBUG(target, "%x is store instruction", instruction);
imm = ((instruction & 0xf80) >> 7) | ((instruction & 0xfe000000) >> 20); imm = ((instruction & 0xf80) >> 7) | ((instruction & 0xfe000000) >> 20);
} else { } else {
LOG_DEBUG("%x is load instruction", instruction); LOG_TARGET_DEBUG(target, "%x is load instruction", instruction);
imm = (instruction & 0xfff00000) >> 20; imm = (instruction & 0xfff00000) >> 20;
} }
/* sign extend 12-bit imm to 16-bits */ /* sign extend 12-bit imm to 16-bits */
if (imm & (1 << 11)) if (imm & (1 << 11))
imm |= 0xf000; imm |= 0xf000;
mem_addr += imm; mem_addr += imm;
LOG_DEBUG("memory address=0x%" PRIx64, mem_addr); LOG_TARGET_DEBUG(target, "Memory address=0x%" PRIx64, mem_addr);
} else { } else {
LOG_DEBUG("%x is not a RV32I load or store", instruction); LOG_TARGET_DEBUG(target, "%x is not a RV32I load or store", instruction);
return ERROR_FAIL; return ERROR_FAIL;
} }
@ -1463,7 +1464,7 @@ static int riscv_hit_watchpoint(struct target *target, struct watchpoint **hit_w
/*TODO support length/mask */ /*TODO support length/mask */
if (wp->address == mem_addr) { if (wp->address == mem_addr) {
*hit_watchpoint = wp; *hit_watchpoint = wp;
LOG_DEBUG("Hit address=%" TARGET_PRIxADDR, wp->address); LOG_TARGET_DEBUG(target, "Hit address=%" TARGET_PRIxADDR, wp->address);
return ERROR_OK; return ERROR_OK;
} }
wp = wp->next; wp = wp->next;
@ -1488,7 +1489,7 @@ static int old_or_new_riscv_step(struct target *target, int current,
target_addr_t address, int handle_breakpoints) target_addr_t address, int handle_breakpoints)
{ {
RISCV_INFO(r); RISCV_INFO(r);
LOG_DEBUG("handle_breakpoints=%d", handle_breakpoints); LOG_TARGET_DEBUG(target, "handle_breakpoints=%d", handle_breakpoints);
if (!r->get_hart_state) if (!r->get_hart_state)
return oldriscv_step(target, current, address, handle_breakpoints); return oldriscv_step(target, current, address, handle_breakpoints);
else else
@ -1497,9 +1498,9 @@ static int old_or_new_riscv_step(struct target *target, int current,
static int riscv_examine(struct target *target) static int riscv_examine(struct target *target)
{ {
LOG_DEBUG("[%s]", target_name(target)); LOG_TARGET_DEBUG(target, "Starting examination");
if (target_was_examined(target)) { if (target_was_examined(target)) {
LOG_DEBUG("Target was already examined."); LOG_TARGET_DEBUG(target, "Target was already examined.");
return ERROR_OK; return ERROR_OK;
} }
@ -1507,9 +1508,9 @@ static int riscv_examine(struct target *target)
RISCV_INFO(info); RISCV_INFO(info);
uint32_t dtmcontrol = dtmcontrol_scan(target, 0); uint32_t dtmcontrol = dtmcontrol_scan(target, 0);
LOG_DEBUG("dtmcontrol=0x%x", dtmcontrol); LOG_TARGET_DEBUG(target, "dtmcontrol=0x%x", dtmcontrol);
info->dtm_version = get_field(dtmcontrol, DTMCONTROL_VERSION); info->dtm_version = get_field(dtmcontrol, DTMCONTROL_VERSION);
LOG_DEBUG(" version=0x%x", info->dtm_version); LOG_TARGET_DEBUG(target, "version=0x%x", info->dtm_version);
struct target_type *tt = get_target_type(target); struct target_type *tt = get_target_type(target);
if (!tt) if (!tt)
@ -1609,7 +1610,7 @@ static int set_debug_reason(struct target *target, enum riscv_halt_reason halt_r
case RISCV_HALT_ERROR: case RISCV_HALT_ERROR:
return ERROR_FAIL; return ERROR_FAIL;
} }
LOG_DEBUG("[%s] debug_reason=%d", target_name(target), target->debug_reason); LOG_TARGET_DEBUG(target, "debug_reason=%d", target->debug_reason);
return ERROR_OK; return ERROR_OK;
} }
@ -1618,8 +1619,7 @@ static int halt_prep(struct target *target)
{ {
RISCV_INFO(r); RISCV_INFO(r);
LOG_DEBUG("[%s] prep hart, debug_reason=%d", target_name(target), LOG_TARGET_DEBUG(target, "prep hart, debug_reason=%d", target->debug_reason);
target->debug_reason);
r->prepped = false; r->prepped = false;
if (target->state == TARGET_HALTED) { if (target->state == TARGET_HALTED) {
LOG_TARGET_DEBUG(target, "Hart is already halted."); LOG_TARGET_DEBUG(target, "Hart is already halted.");
@ -1642,7 +1642,7 @@ static int riscv_halt_go_all_harts(struct target *target)
if (riscv_get_hart_state(target, &state) != ERROR_OK) if (riscv_get_hart_state(target, &state) != ERROR_OK)
return ERROR_FAIL; return ERROR_FAIL;
if (state == RISCV_STATE_HALTED) { if (state == RISCV_STATE_HALTED) {
LOG_DEBUG("[%s] Hart is already halted.", target_name(target)); LOG_TARGET_DEBUG(target, "Hart is already halted.");
} else { } else {
if (r->halt_go(target) != ERROR_OK) if (r->halt_go(target) != ERROR_OK)
return ERROR_FAIL; return ERROR_FAIL;
@ -1723,7 +1723,7 @@ int riscv_halt(struct target *target)
static int riscv_assert_reset(struct target *target) static int riscv_assert_reset(struct target *target)
{ {
LOG_DEBUG("[%d]", target->coreid); LOG_TARGET_DEBUG(target, "coreid: [%d]", target->coreid);
struct target_type *tt = get_target_type(target); struct target_type *tt = get_target_type(target);
riscv_invalidate_register_cache(target); riscv_invalidate_register_cache(target);
return tt->assert_reset(target); return tt->assert_reset(target);
@ -1731,7 +1731,7 @@ static int riscv_assert_reset(struct target *target)
static int riscv_deassert_reset(struct target *target) static int riscv_deassert_reset(struct target *target)
{ {
LOG_DEBUG("[%d]", target->coreid); LOG_TARGET_DEBUG(target, "coreid: [%d]", target->coreid);
struct target_type *tt = get_target_type(target); struct target_type *tt = get_target_type(target);
return tt->deassert_reset(target); return tt->deassert_reset(target);
} }
@ -1741,7 +1741,7 @@ static int disable_triggers(struct target *target, riscv_reg_t *state)
{ {
RISCV_INFO(r); RISCV_INFO(r);
LOG_DEBUG("deal with triggers"); LOG_TARGET_DEBUG(target, "Disabling triggers.");
if (riscv_enumerate_triggers(target) != ERROR_OK) if (riscv_enumerate_triggers(target) != ERROR_OK)
return ERROR_FAIL; return ERROR_FAIL;
@ -1771,7 +1771,7 @@ static int disable_triggers(struct target *target, riscv_reg_t *state)
struct watchpoint *watchpoint = target->watchpoints; struct watchpoint *watchpoint = target->watchpoints;
int i = 0; int i = 0;
while (watchpoint) { while (watchpoint) {
LOG_DEBUG("watchpoint %d: set=%d", i, watchpoint->is_set); LOG_TARGET_DEBUG(target, "Watchpoint %d: set=%d", i, watchpoint->is_set);
state[i] = watchpoint->is_set; state[i] = watchpoint->is_set;
if (watchpoint->is_set) { if (watchpoint->is_set) {
if (riscv_remove_watchpoint(target, watchpoint) != ERROR_OK) if (riscv_remove_watchpoint(target, watchpoint) != ERROR_OK)
@ -1809,7 +1809,7 @@ static int enable_triggers(struct target *target, riscv_reg_t *state)
struct watchpoint *watchpoint = target->watchpoints; struct watchpoint *watchpoint = target->watchpoints;
int i = 0; int i = 0;
while (watchpoint) { while (watchpoint) {
LOG_DEBUG("watchpoint %d: cleared=%" PRId64, i, state[i]); LOG_TARGET_DEBUG(target, "Watchpoint %d: cleared=%" PRId64, i, state[i]);
if (state[i]) { if (state[i]) {
if (riscv_add_watchpoint(target, watchpoint) != ERROR_OK) if (riscv_add_watchpoint(target, watchpoint) != ERROR_OK)
return ERROR_FAIL; return ERROR_FAIL;
@ -1847,7 +1847,7 @@ static int resume_prep(struct target *target, int current,
return ERROR_FAIL; return ERROR_FAIL;
} }
LOG_DEBUG("[%d] mark as prepped", target->coreid); LOG_TARGET_DEBUG(target, "Mark as prepped.");
r->prepped = true; r->prepped = true;
return ERROR_OK; return ERROR_OK;
@ -1959,7 +1959,7 @@ static int riscv_target_resume(struct target *target, int current,
target_addr_t address, int handle_breakpoints, int debug_execution) target_addr_t address, int handle_breakpoints, int debug_execution)
{ {
if (target->state != TARGET_HALTED) { if (target->state != TARGET_HALTED) {
LOG_TARGET_ERROR(target, "not halted"); LOG_TARGET_ERROR(target, "Not halted.");
return ERROR_TARGET_NOT_HALTED; return ERROR_TARGET_NOT_HALTED;
} }
return riscv_resume(target, current, address, handle_breakpoints, return riscv_resume(target, current, address, handle_breakpoints,
@ -2001,7 +2001,7 @@ static int riscv_mmu(struct target *target, int *enabled)
/* Don't use MMU in explicit or effective M (machine) mode */ /* Don't use MMU in explicit or effective M (machine) mode */
riscv_reg_t priv; riscv_reg_t priv;
if (riscv_get_register(target, &priv, GDB_REGNO_PRIV) != ERROR_OK) { if (riscv_get_register(target, &priv, GDB_REGNO_PRIV) != ERROR_OK) {
LOG_ERROR("Failed to read priv register."); LOG_TARGET_ERROR(target, "Failed to read priv register.");
return ERROR_FAIL; return ERROR_FAIL;
} }
@ -2019,7 +2019,7 @@ static int riscv_mmu(struct target *target, int *enabled)
if (effective_mode == PRV_U) { if (effective_mode == PRV_U) {
riscv_reg_t hstatus; riscv_reg_t hstatus;
if (riscv_get_register(target, &hstatus, GDB_REGNO_HSTATUS) != ERROR_OK) { if (riscv_get_register(target, &hstatus, GDB_REGNO_HSTATUS) != ERROR_OK) {
LOG_ERROR("Failed to read hstatus register."); LOG_TARGET_ERROR(target, "Failed to read hstatus register.");
return ERROR_FAIL; return ERROR_FAIL;
} }
@ -2068,17 +2068,17 @@ static int riscv_mmu(struct target *target, int *enabled)
riscv_reg_t satp; riscv_reg_t satp;
if (riscv_get_register(target, &satp, GDB_REGNO_SATP) != ERROR_OK) { if (riscv_get_register(target, &satp, GDB_REGNO_SATP) != ERROR_OK) {
LOG_DEBUG("Couldn't read SATP."); LOG_TARGET_DEBUG(target, "Couldn't read SATP.");
/* If we can't read SATP, then there must not be an MMU. */ /* If we can't read SATP, then there must not be an MMU. */
*enabled = 0; *enabled = 0;
return ERROR_OK; return ERROR_OK;
} }
if (get_field(satp, RISCV_SATP_MODE(xlen)) == SATP_MODE_OFF) { if (get_field(satp, RISCV_SATP_MODE(xlen)) == SATP_MODE_OFF) {
LOG_DEBUG("MMU is disabled."); LOG_TARGET_DEBUG(target, "MMU is disabled.");
*enabled = 0; *enabled = 0;
} else { } else {
LOG_DEBUG("MMU is enabled."); LOG_TARGET_DEBUG(target, "MMU is enabled.");
*enabled = 1; *enabled = 1;
} }
@ -2104,7 +2104,7 @@ static int riscv_address_translate(struct target *target,
target_addr_t mask = ((target_addr_t)1 << (xlen - (info->va_bits - 1))) - 1; target_addr_t mask = ((target_addr_t)1 << (xlen - (info->va_bits - 1))) - 1;
target_addr_t masked_msbs = (virtual >> (info->va_bits - 1)) & mask; target_addr_t masked_msbs = (virtual >> (info->va_bits - 1)) & mask;
if (masked_msbs != 0 && masked_msbs != mask) { if (masked_msbs != 0 && masked_msbs != mask) {
LOG_ERROR("Virtual address 0x%" TARGET_PRIxADDR " is not sign-extended " LOG_TARGET_ERROR(target, "Virtual address 0x%" TARGET_PRIxADDR " is not sign-extended "
"for %s mode.", virtual, info->name); "for %s mode.", virtual, info->name);
return ERROR_FAIL; return ERROR_FAIL;
} }
@ -2136,7 +2136,7 @@ static int riscv_address_translate(struct target *target,
else else
pte = buf_get_u64(buffer, 0, 64); pte = buf_get_u64(buffer, 0, 64);
LOG_DEBUG("i=%d; PTE @0x%" TARGET_PRIxADDR " = 0x%" PRIx64, i, LOG_TARGET_DEBUG(target, "i=%d; PTE @0x%" TARGET_PRIxADDR " = 0x%" PRIx64, i,
pte_address, pte); pte_address, pte);
if (!(pte & PTE_V) || (!(pte & PTE_R) && (pte & PTE_W))) { if (!(pte & PTE_V) || (!(pte & PTE_R) && (pte & PTE_W))) {
@ -2156,7 +2156,7 @@ static int riscv_address_translate(struct target *target,
} }
if (i < 0) { if (i < 0) {
LOG_ERROR("Couldn't find the PTE."); LOG_TARGET_ERROR(target, "Couldn't find the PTE.");
return ERROR_FAIL; return ERROR_FAIL;
} }
@ -2288,7 +2288,7 @@ static int riscv_virt2phys(struct target *target, target_addr_t virtual, target_
riscv_reg_t priv; riscv_reg_t priv;
if (riscv_get_register(target, &priv, GDB_REGNO_PRIV) != ERROR_OK) { if (riscv_get_register(target, &priv, GDB_REGNO_PRIV) != ERROR_OK) {
LOG_ERROR("Failed to read priv register."); LOG_TARGET_ERROR(target, "Failed to read priv register.");
return ERROR_FAIL; return ERROR_FAIL;
} }
@ -2314,11 +2314,11 @@ static int riscv_virt2phys(struct target *target, target_addr_t virtual, target_
satp_info = &sv48; satp_info = &sv48;
break; break;
case SATP_MODE_OFF: case SATP_MODE_OFF:
LOG_ERROR("No translation or protection." LOG_TARGET_ERROR(target, "No translation or protection."
" (satp: 0x%" PRIx64 ")", satp_value); " (satp: 0x%" PRIx64 ")", satp_value);
return ERROR_FAIL; return ERROR_FAIL;
default: default:
LOG_ERROR("The translation mode is not supported." LOG_TARGET_ERROR(target, "The translation mode is not supported."
" (satp: 0x%" PRIx64 ")", satp_value); " (satp: 0x%" PRIx64 ")", satp_value);
return ERROR_FAIL; return ERROR_FAIL;
} }
@ -2340,7 +2340,7 @@ static int riscv_read_memory(struct target *target, target_addr_t address,
uint32_t size, uint32_t count, uint8_t *buffer) uint32_t size, uint32_t count, uint8_t *buffer)
{ {
if (count == 0) { if (count == 0) {
LOG_WARNING("0-length read from 0x%" TARGET_PRIxADDR, address); LOG_TARGET_WARNING(target, "0-length read from 0x%" TARGET_PRIxADDR, address);
return ERROR_OK; return ERROR_OK;
} }
@ -2363,7 +2363,7 @@ static int riscv_write_memory(struct target *target, target_addr_t address,
uint32_t size, uint32_t count, const uint8_t *buffer) uint32_t size, uint32_t count, const uint8_t *buffer)
{ {
if (count == 0) { if (count == 0) {
LOG_WARNING("0-length write to 0x%" TARGET_PRIxADDR, address); LOG_TARGET_WARNING(target, "0-length write to 0x%" TARGET_PRIxADDR, address);
return ERROR_OK; return ERROR_OK;
} }
@ -2383,7 +2383,7 @@ static const char *riscv_get_gdb_arch(struct target *target)
case 64: case 64:
return "riscv:rv64"; return "riscv:rv64";
} }
LOG_ERROR("Unsupported xlen: %d", riscv_xlen(target)); LOG_TARGET_ERROR(target, "Unsupported xlen: %d", riscv_xlen(target));
return NULL; return NULL;
} }
@ -2394,7 +2394,7 @@ static int riscv_get_gdb_reg_list_internal(struct target *target,
LOG_TARGET_DEBUG(target, "reg_class=%d, read=%d", reg_class, is_read); LOG_TARGET_DEBUG(target, "reg_class=%d, read=%d", reg_class, is_read);
if (!target->reg_cache) { if (!target->reg_cache) {
LOG_ERROR("Target not initialized. Return ERROR_FAIL."); LOG_TARGET_ERROR(target, "Target not initialized. Return ERROR_FAIL.");
return ERROR_FAIL; return ERROR_FAIL;
} }
@ -2406,7 +2406,7 @@ static int riscv_get_gdb_reg_list_internal(struct target *target,
*reg_list_size = target->reg_cache->num_regs; *reg_list_size = target->reg_cache->num_regs;
break; break;
default: default:
LOG_ERROR("Unsupported reg_class: %d", reg_class); LOG_TARGET_ERROR(target, "Unsupported reg_class: %d", reg_class);
return ERROR_FAIL; return ERROR_FAIL;
} }
@ -2461,7 +2461,7 @@ static int riscv_run_algorithm(struct target *target, int num_mem_params,
RISCV_INFO(info); RISCV_INFO(info);
if (target->state != TARGET_HALTED) { if (target->state != TARGET_HALTED) {
LOG_WARNING("target not halted"); LOG_TARGET_WARNING(target, "Target not halted.");
return ERROR_TARGET_NOT_HALTED; return ERROR_TARGET_NOT_HALTED;
} }
@ -2471,8 +2471,8 @@ static int riscv_run_algorithm(struct target *target, int num_mem_params,
mem_params[i].direction == PARAM_IN_OUT) { mem_params[i].direction == PARAM_IN_OUT) {
int retval = target_write_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value); int retval = target_write_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value);
if (retval != ERROR_OK) { if (retval != ERROR_OK) {
LOG_ERROR("Couldn't write input mem param into the memory, addr=0x%" TARGET_PRIxADDR " size=0x%" PRIx32, LOG_TARGET_ERROR(target, "Couldn't write input mem param into the memory, addr=0x%" TARGET_PRIxADDR
mem_params[i].address, mem_params[i].size); " size=0x%" PRIx32, mem_params[i].address, mem_params[i].size);
return retval; return retval;
} }
} }
@ -2483,25 +2483,25 @@ static int riscv_run_algorithm(struct target *target, int num_mem_params,
if (!reg_pc || reg_pc->type->get(reg_pc) != ERROR_OK) if (!reg_pc || reg_pc->type->get(reg_pc) != ERROR_OK)
return ERROR_FAIL; return ERROR_FAIL;
uint64_t saved_pc = buf_get_u64(reg_pc->value, 0, reg_pc->size); uint64_t saved_pc = buf_get_u64(reg_pc->value, 0, reg_pc->size);
LOG_DEBUG("saved_pc=0x%" PRIx64, saved_pc); LOG_TARGET_DEBUG(target, "saved_pc=0x%" PRIx64, saved_pc);
uint64_t saved_regs[32]; uint64_t saved_regs[32];
for (int i = 0; i < num_reg_params; i++) { for (int i = 0; i < num_reg_params; i++) {
LOG_DEBUG("save %s", reg_params[i].reg_name); LOG_TARGET_DEBUG(target, "save %s", reg_params[i].reg_name);
struct reg *r = register_get_by_name(target->reg_cache, reg_params[i].reg_name, false); struct reg *r = register_get_by_name(target->reg_cache, reg_params[i].reg_name, false);
if (!r) { if (!r) {
LOG_ERROR("Couldn't find register named '%s'", reg_params[i].reg_name); LOG_TARGET_ERROR(target, "Couldn't find register named '%s'", reg_params[i].reg_name);
return ERROR_FAIL; return ERROR_FAIL;
} }
if (r->size != reg_params[i].size) { if (r->size != reg_params[i].size) {
LOG_ERROR("Register %s is %d bits instead of %d bits.", LOG_TARGET_ERROR(target, "Register %s is %d bits instead of %d bits.",
reg_params[i].reg_name, r->size, reg_params[i].size); reg_params[i].reg_name, r->size, reg_params[i].size);
return ERROR_FAIL; return ERROR_FAIL;
} }
if (r->number > GDB_REGNO_XPR31) { if (r->number > GDB_REGNO_XPR31) {
LOG_ERROR("Only GPRs can be use as argument registers."); LOG_TARGET_ERROR(target, "Only GPRs can be use as argument registers.");
return ERROR_FAIL; return ERROR_FAIL;
} }
@ -2522,16 +2522,16 @@ static int riscv_run_algorithm(struct target *target, int num_mem_params,
return ERROR_FAIL; return ERROR_FAIL;
/* Run algorithm */ /* Run algorithm */
LOG_DEBUG("resume at 0x%" TARGET_PRIxADDR, entry_point); LOG_TARGET_DEBUG(target, "Resume at 0x%" TARGET_PRIxADDR, entry_point);
if (riscv_resume(target, 0, entry_point, 0, 1, true) != ERROR_OK) if (riscv_resume(target, 0, entry_point, 0, 1, true) != ERROR_OK)
return ERROR_FAIL; return ERROR_FAIL;
int64_t start = timeval_ms(); int64_t start = timeval_ms();
while (target->state != TARGET_HALTED) { while (target->state != TARGET_HALTED) {
LOG_DEBUG("poll()"); LOG_TARGET_DEBUG(target, "poll()");
int64_t now = timeval_ms(); int64_t now = timeval_ms();
if (now - start > timeout_ms) { if (now - start > timeout_ms) {
LOG_ERROR("Algorithm timed out after %" PRId64 " ms.", now - start); LOG_TARGET_ERROR(target, "Algorithm timed out after %" PRId64 " ms.", now - start);
riscv_halt(target); riscv_halt(target);
old_or_new_riscv_poll(target); old_or_new_riscv_poll(target);
enum gdb_regno regnums[] = { enum gdb_regno regnums[] = {
@ -2551,7 +2551,7 @@ static int riscv_run_algorithm(struct target *target, int num_mem_params,
riscv_reg_t reg_value; riscv_reg_t reg_value;
if (riscv_get_register(target, &reg_value, regno) != ERROR_OK) if (riscv_get_register(target, &reg_value, regno) != ERROR_OK)
break; break;
LOG_ERROR("%s = 0x%" PRIx64, gdb_regno_name(regno), reg_value); LOG_TARGET_ERROR(target, "%s = 0x%" PRIx64, gdb_regno_name(regno), reg_value);
} }
return ERROR_TARGET_TIMEOUT; return ERROR_TARGET_TIMEOUT;
} }
@ -2569,7 +2569,7 @@ static int riscv_run_algorithm(struct target *target, int num_mem_params,
return ERROR_FAIL; return ERROR_FAIL;
uint64_t final_pc = buf_get_u64(reg_pc->value, 0, reg_pc->size); uint64_t final_pc = buf_get_u64(reg_pc->value, 0, reg_pc->size);
if (exit_point && final_pc != exit_point) { if (exit_point && final_pc != exit_point) {
LOG_ERROR("PC ended up at 0x%" PRIx64 " instead of 0x%" LOG_TARGET_ERROR(target, "PC ended up at 0x%" PRIx64 " instead of 0x%"
TARGET_PRIxADDR, final_pc, exit_point); TARGET_PRIxADDR, final_pc, exit_point);
return ERROR_FAIL; return ERROR_FAIL;
} }
@ -2589,16 +2589,16 @@ static int riscv_run_algorithm(struct target *target, int num_mem_params,
reg_params[i].direction == PARAM_IN_OUT) { reg_params[i].direction == PARAM_IN_OUT) {
struct reg *r = register_get_by_name(target->reg_cache, reg_params[i].reg_name, false); struct reg *r = register_get_by_name(target->reg_cache, reg_params[i].reg_name, false);
if (r->type->get(r) != ERROR_OK) { if (r->type->get(r) != ERROR_OK) {
LOG_ERROR("get(%s) failed", r->name); LOG_TARGET_ERROR(target, "get(%s) failed", r->name);
return ERROR_FAIL; return ERROR_FAIL;
} }
buf_cpy(r->value, reg_params[i].value, reg_params[i].size); buf_cpy(r->value, reg_params[i].value, reg_params[i].size);
} }
LOG_DEBUG("restore %s", reg_params[i].reg_name); LOG_TARGET_DEBUG(target, "restore %s", reg_params[i].reg_name);
struct reg *r = register_get_by_name(target->reg_cache, reg_params[i].reg_name, false); struct reg *r = register_get_by_name(target->reg_cache, reg_params[i].reg_name, false);
buf_set_u64(buf, 0, info->xlen, saved_regs[r->number]); buf_set_u64(buf, 0, info->xlen, saved_regs[r->number]);
if (r->type->set(r, buf) != ERROR_OK) { if (r->type->set(r, buf) != ERROR_OK) {
LOG_ERROR("set(%s) failed", r->name); LOG_TARGET_ERROR(target, "set(%s) failed", r->name);
return ERROR_FAIL; return ERROR_FAIL;
} }
} }
@ -2610,7 +2610,8 @@ static int riscv_run_algorithm(struct target *target, int num_mem_params,
int retval = target_read_buffer(target, mem_params[i].address, mem_params[i].size, int retval = target_read_buffer(target, mem_params[i].address, mem_params[i].size,
mem_params[i].value); mem_params[i].value);
if (retval != ERROR_OK) { if (retval != ERROR_OK) {
LOG_ERROR("Couldn't read output mem param from the memory, addr=0x%" TARGET_PRIxADDR " size=0x%" PRIx32, LOG_TARGET_ERROR(target, "Couldn't read output mem param from the memory, "
"addr=0x%" TARGET_PRIxADDR " size=0x%" PRIx32,
mem_params[i].address, mem_params[i].size); mem_params[i].address, mem_params[i].size);
return retval; return retval;
} }
@ -2628,7 +2629,7 @@ static int riscv_checksum_memory(struct target *target,
struct reg_param reg_params[2]; struct reg_param reg_params[2];
int retval; int retval;
LOG_DEBUG("address=0x%" TARGET_PRIxADDR "; count=0x%" PRIx32, address, count); LOG_TARGET_DEBUG(target, "address=0x%" TARGET_PRIxADDR "; count=0x%" PRIx32, address, count);
static const uint8_t riscv32_crc_code[] = { static const uint8_t riscv32_crc_code[] = {
#include "../../../contrib/loaders/checksum/riscv32_crc.inc" #include "../../../contrib/loaders/checksum/riscv32_crc.inc"
@ -2672,7 +2673,7 @@ static int riscv_checksum_memory(struct target *target,
retval = target_write_buffer(target, crc_algorithm->address, crc_code_size, retval = target_write_buffer(target, crc_algorithm->address, crc_code_size,
crc_code); crc_code);
if (retval != ERROR_OK) { if (retval != ERROR_OK) {
LOG_ERROR("Failed to write code to " TARGET_ADDR_FMT ": %d", LOG_TARGET_ERROR(target, "Failed to write code to " TARGET_ADDR_FMT ": %d",
crc_algorithm->address, retval); crc_algorithm->address, retval);
target_free_working_area(target, crc_algorithm); target_free_working_area(target, crc_algorithm);
return retval; return retval;
@ -2694,14 +2695,14 @@ static int riscv_checksum_memory(struct target *target,
if (retval == ERROR_OK) if (retval == ERROR_OK)
*checksum = buf_get_u32(reg_params[0].value, 0, 32); *checksum = buf_get_u32(reg_params[0].value, 0, 32);
else else
LOG_ERROR("error executing RISC-V CRC algorithm"); LOG_TARGET_ERROR(target, "Error executing RISC-V CRC algorithm.");
destroy_reg_param(&reg_params[0]); destroy_reg_param(&reg_params[0]);
destroy_reg_param(&reg_params[1]); destroy_reg_param(&reg_params[1]);
target_free_working_area(target, crc_algorithm); target_free_working_area(target, crc_algorithm);
LOG_DEBUG("checksum=0x%" PRIx32 ", result=%d", *checksum, retval); LOG_TARGET_DEBUG(target, "checksum=0x%" PRIx32 ", result=%d", *checksum, retval);
return retval; return retval;
} }
@ -2851,7 +2852,7 @@ static int sample_memory(struct target *target)
if (!r->sample_buf.buf || !r->sample_config.enabled) if (!r->sample_buf.buf || !r->sample_config.enabled)
return ERROR_OK; return ERROR_OK;
LOG_DEBUG("buf used/size: %d/%d", r->sample_buf.used, r->sample_buf.size); LOG_TARGET_DEBUG(target, "buf used/size: %d/%d", r->sample_buf.used, r->sample_buf.size);
uint64_t start = timeval_ms(); uint64_t start = timeval_ms();
riscv_sample_buf_maybe_add_timestamp(target, true); riscv_sample_buf_maybe_add_timestamp(target, true);
@ -2885,7 +2886,7 @@ static int sample_memory(struct target *target)
exit: exit:
riscv_sample_buf_maybe_add_timestamp(target, false); riscv_sample_buf_maybe_add_timestamp(target, false);
if (result != ERROR_OK) { if (result != ERROR_OK) {
LOG_INFO("Turning off memory sampling because it failed."); LOG_TARGET_INFO(target, "Turning off memory sampling because it failed.");
r->sample_config.enabled = false; r->sample_config.enabled = false;
} }
return result; return result;
@ -2894,7 +2895,7 @@ exit:
/*** OpenOCD Interface ***/ /*** OpenOCD Interface ***/
int riscv_openocd_poll(struct target *target) int riscv_openocd_poll(struct target *target)
{ {
LOG_DEBUG("polling all harts"); LOG_TARGET_DEBUG(target, "Polling all harts.");
struct list_head *targets; struct list_head *targets;
@ -2950,10 +2951,10 @@ int riscv_openocd_poll(struct target *target)
} }
} }
LOG_DEBUG("should_remain_halted=%d, should_resume=%d", LOG_TARGET_DEBUG(target, "should_remain_halted=%d, should_resume=%d",
should_remain_halted, should_resume); should_remain_halted, should_resume);
if (should_remain_halted && should_resume) { if (should_remain_halted && should_resume) {
LOG_WARNING("%d harts should remain halted, and %d should resume.", LOG_TARGET_WARNING(target, "%d harts should remain halted, and %d should resume.",
should_remain_halted, should_resume); should_remain_halted, should_resume);
} }
if (should_remain_halted) { if (should_remain_halted) {
@ -3040,14 +3041,14 @@ int riscv_openocd_step(struct target *target, int current,
if (riscv_interrupts_disable(target, irq_disabled_mask, if (riscv_interrupts_disable(target, irq_disabled_mask,
&current_mstatus) != ERROR_OK) { &current_mstatus) != ERROR_OK) {
success = false; success = false;
LOG_ERROR("unable to disable interrupts"); LOG_TARGET_ERROR(target, "Unable to disable interrupts.");
goto _exit; goto _exit;
} }
} }
if (riscv_step_rtos_hart(target) != ERROR_OK) { if (riscv_step_rtos_hart(target) != ERROR_OK) {
success = false; success = false;
LOG_ERROR("unable to step rtos hart"); LOG_TARGET_ERROR(target, "Unable to step rtos hart.");
} }
register_cache_invalidate(target->reg_cache); register_cache_invalidate(target->reg_cache);
@ -3055,18 +3056,18 @@ int riscv_openocd_step(struct target *target, int current,
if (info->isrmask_mode == RISCV_ISRMASK_STEPONLY) if (info->isrmask_mode == RISCV_ISRMASK_STEPONLY)
if (riscv_interrupts_restore(target, current_mstatus) != ERROR_OK) { if (riscv_interrupts_restore(target, current_mstatus) != ERROR_OK) {
success = false; success = false;
LOG_ERROR("unable to restore interrupts"); LOG_TARGET_ERROR(target, "Unable to restore interrupts.");
} }
_exit: _exit:
if (enable_triggers(target, trigger_state) != ERROR_OK) { if (enable_triggers(target, trigger_state) != ERROR_OK) {
success = false; success = false;
LOG_ERROR("unable to enable triggers"); LOG_TARGET_ERROR(target, "Unable to enable triggers.");
} }
if (breakpoint && (riscv_add_breakpoint(target, breakpoint) != ERROR_OK)) { if (breakpoint && (riscv_add_breakpoint(target, breakpoint) != ERROR_OK)) {
success = false; success = false;
LOG_TARGET_ERROR(target, "unable to restore the disabled breakpoint"); LOG_TARGET_ERROR(target, "Unable to restore the disabled breakpoint.");
} }
if (success) { if (success) {
@ -3083,7 +3084,7 @@ _exit:
COMMAND_HANDLER(riscv_set_command_timeout_sec) COMMAND_HANDLER(riscv_set_command_timeout_sec)
{ {
if (CMD_ARGC != 1) { if (CMD_ARGC != 1) {
LOG_ERROR("Command takes exactly 1 parameter"); LOG_ERROR("Command takes exactly 1 parameter.");
return ERROR_COMMAND_SYNTAX_ERROR; return ERROR_COMMAND_SYNTAX_ERROR;
} }
int timeout = atoi(CMD_ARGV[0]); int timeout = atoi(CMD_ARGV[0]);
@ -3100,7 +3101,7 @@ COMMAND_HANDLER(riscv_set_command_timeout_sec)
COMMAND_HANDLER(riscv_set_reset_timeout_sec) COMMAND_HANDLER(riscv_set_reset_timeout_sec)
{ {
if (CMD_ARGC != 1) { if (CMD_ARGC != 1) {
LOG_ERROR("Command takes exactly 1 parameter"); LOG_ERROR("Command takes exactly 1 parameter.");
return ERROR_COMMAND_SYNTAX_ERROR; return ERROR_COMMAND_SYNTAX_ERROR;
} }
int timeout = atoi(CMD_ARGV[0]); int timeout = atoi(CMD_ARGV[0]);
@ -3334,7 +3335,7 @@ static int parse_ranges(struct list_head *ranges, const char *tcl_arg, const cha
COMMAND_HANDLER(riscv_set_expose_csrs) COMMAND_HANDLER(riscv_set_expose_csrs)
{ {
if (CMD_ARGC == 0) { if (CMD_ARGC == 0) {
LOG_ERROR("Command expects parameters"); LOG_ERROR("Command expects parameters.");
return ERROR_COMMAND_SYNTAX_ERROR; return ERROR_COMMAND_SYNTAX_ERROR;
} }
@ -3354,7 +3355,7 @@ COMMAND_HANDLER(riscv_set_expose_csrs)
COMMAND_HANDLER(riscv_set_expose_custom) COMMAND_HANDLER(riscv_set_expose_custom)
{ {
if (CMD_ARGC == 0) { if (CMD_ARGC == 0) {
LOG_ERROR("Command expects parameters"); LOG_ERROR("Command expects parameters.");
return ERROR_COMMAND_SYNTAX_ERROR; return ERROR_COMMAND_SYNTAX_ERROR;
} }
@ -3399,7 +3400,7 @@ COMMAND_HANDLER(riscv_authdata_read)
} else if (CMD_ARGC == 1) { } else if (CMD_ARGC == 1) {
COMMAND_PARSE_NUMBER(uint, CMD_ARGV[0], index); COMMAND_PARSE_NUMBER(uint, CMD_ARGV[0], index);
} else { } else {
LOG_ERROR("Command takes at most one parameter"); LOG_ERROR("Command takes at most one parameter.");
return ERROR_COMMAND_SYNTAX_ERROR; return ERROR_COMMAND_SYNTAX_ERROR;
} }
@ -3411,7 +3412,7 @@ COMMAND_HANDLER(riscv_authdata_read)
RISCV_INFO(r); RISCV_INFO(r);
if (!r) { if (!r) {
LOG_ERROR("riscv_info is NULL!"); LOG_TARGET_ERROR(target, "riscv_info is NULL!");
return ERROR_FAIL; return ERROR_FAIL;
} }
@ -3422,7 +3423,7 @@ COMMAND_HANDLER(riscv_authdata_read)
command_print_sameline(CMD, "0x%08" PRIx32, value); command_print_sameline(CMD, "0x%08" PRIx32, value);
return ERROR_OK; return ERROR_OK;
} else { } else {
LOG_ERROR("authdata_read is not implemented for this target."); LOG_TARGET_ERROR(target, "authdata_read is not implemented for this target.");
return ERROR_FAIL; return ERROR_FAIL;
} }
} }
@ -3446,7 +3447,7 @@ COMMAND_HANDLER(riscv_authdata_write)
RISCV_INFO(r); RISCV_INFO(r);
if (!r->authdata_write) { if (!r->authdata_write) {
LOG_ERROR("authdata_write is not implemented for this target."); LOG_TARGET_ERROR(target, "authdata_write is not implemented for this target.");
return ERROR_FAIL; return ERROR_FAIL;
} }
@ -3468,7 +3469,7 @@ COMMAND_HANDLER(riscv_dmi_read)
RISCV_INFO(r); RISCV_INFO(r);
if (!r) { if (!r) {
LOG_ERROR("riscv_info is NULL!"); LOG_TARGET_ERROR(target, "riscv_info is NULL!");
return ERROR_FAIL; return ERROR_FAIL;
} }
@ -3480,7 +3481,7 @@ COMMAND_HANDLER(riscv_dmi_read)
command_print(CMD, "0x%" PRIx32, value); command_print(CMD, "0x%" PRIx32, value);
return ERROR_OK; return ERROR_OK;
} else { } else {
LOG_ERROR("dmi_read is not implemented for this target."); LOG_TARGET_ERROR(target, "dmi_read is not implemented for this target.");
return ERROR_FAIL; return ERROR_FAIL;
} }
} }
@ -3519,7 +3520,7 @@ COMMAND_HANDLER(riscv_dmi_write)
return retval; return retval;
} }
LOG_ERROR("dmi_write is not implemented for this target."); LOG_TARGET_ERROR(target, "dmi_write is not implemented for this target.");
return ERROR_FAIL; return ERROR_FAIL;
} }
@ -3625,7 +3626,6 @@ COMMAND_HANDLER(riscv_set_bscan_tunnel_ir)
return ERROR_OK; return ERROR_OK;
} }
COMMAND_HANDLER(riscv_set_maskisr) COMMAND_HANDLER(riscv_set_maskisr)
{ {
struct target *target = get_current_target(CMD_CTX); struct target *target = get_current_target(CMD_CTX);
@ -3969,7 +3969,7 @@ COMMAND_HANDLER(handle_memory_sample_command)
uint32_t bucket; uint32_t bucket;
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], bucket); COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], bucket);
if (bucket > ARRAY_SIZE(r->sample_config.bucket)) { if (bucket > ARRAY_SIZE(r->sample_config.bucket)) {
LOG_ERROR("Max bucket number is %zu.", ARRAY_SIZE(r->sample_config.bucket)); LOG_TARGET_ERROR(target, "Max bucket number is %zd.", ARRAY_SIZE(r->sample_config.bucket));
return ERROR_COMMAND_ARGUMENT_INVALID; return ERROR_COMMAND_ARGUMENT_INVALID;
} }
@ -3982,7 +3982,7 @@ COMMAND_HANDLER(handle_memory_sample_command)
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], r->sample_config.bucket[bucket].size_bytes); COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], r->sample_config.bucket[bucket].size_bytes);
if (r->sample_config.bucket[bucket].size_bytes != 4 && if (r->sample_config.bucket[bucket].size_bytes != 4 &&
r->sample_config.bucket[bucket].size_bytes != 8) { r->sample_config.bucket[bucket].size_bytes != 8) {
LOG_ERROR("Only 4-byte and 8-byte sizes are supported."); LOG_TARGET_ERROR(target, "Only 4-byte and 8-byte sizes are supported.");
return ERROR_COMMAND_ARGUMENT_INVALID; return ERROR_COMMAND_ARGUMENT_INVALID;
} }
} else { } else {
@ -4029,7 +4029,7 @@ COMMAND_HANDLER(handle_dump_sample_buf_command)
unsigned char *encoded = base64_encode(r->sample_buf.buf, unsigned char *encoded = base64_encode(r->sample_buf.buf,
r->sample_buf.used, NULL); r->sample_buf.used, NULL);
if (!encoded) { if (!encoded) {
LOG_ERROR("Failed base64 encode!"); LOG_TARGET_ERROR(target, "Failed base64 encode!");
result = ERROR_FAIL; result = ERROR_FAIL;
goto error; goto error;
} }
@ -4059,13 +4059,13 @@ COMMAND_HANDLER(handle_dump_sample_buf_command)
i += 8; i += 8;
command_print(CMD, "0x%016" PRIx64, value); command_print(CMD, "0x%016" PRIx64, value);
} else { } else {
LOG_ERROR("Found invalid size in bucket %d: %d", command, LOG_TARGET_ERROR(target, "Found invalid size in bucket %d: %d", command,
r->sample_config.bucket[command].size_bytes); r->sample_config.bucket[command].size_bytes);
result = ERROR_FAIL; result = ERROR_FAIL;
goto error; goto error;
} }
} else { } else {
LOG_ERROR("Found invalid command byte in sample buf: 0x%2x at offset 0x%x", LOG_TARGET_ERROR(target, "Found invalid command byte in sample buf: 0x%2x at offset 0x%x",
command, i - 1); command, i - 1);
result = ERROR_FAIL; result = ERROR_FAIL;
goto error; goto error;
@ -4536,13 +4536,12 @@ static int riscv_resume_go_all_harts(struct target *target)
{ {
RISCV_INFO(r); RISCV_INFO(r);
LOG_TARGET_DEBUG(target, "resuming hart, state=%d", target->state); LOG_TARGET_DEBUG(target, "Resuming hart, state=%d.", target->state);
if (target->state == TARGET_HALTED) { if (target->state == TARGET_HALTED) {
if (r->resume_go(target) != ERROR_OK) if (r->resume_go(target) != ERROR_OK)
return ERROR_FAIL; return ERROR_FAIL;
} else { } else {
LOG_DEBUG("[%s] hart requested resume, but was already resumed", LOG_TARGET_DEBUG(target, "Hart requested resume, but was already resumed.");
target_name(target));
} }
riscv_invalidate_register_cache(target); riscv_invalidate_register_cache(target);
@ -4551,11 +4550,11 @@ static int riscv_resume_go_all_harts(struct target *target)
int riscv_interrupts_disable(struct target *target, uint64_t irq_mask, uint64_t *old_mstatus) int riscv_interrupts_disable(struct target *target, uint64_t irq_mask, uint64_t *old_mstatus)
{ {
LOG_DEBUG("Disabling Interrupts"); LOG_TARGET_DEBUG(target, "Disabling interrupts.");
struct reg *reg_mstatus = register_get_by_name(target->reg_cache, struct reg *reg_mstatus = register_get_by_name(target->reg_cache,
"mstatus", true); "mstatus", true);
if (!reg_mstatus) { if (!reg_mstatus) {
LOG_ERROR("Couldn't find mstatus!"); LOG_TARGET_ERROR(target, "Couldn't find mstatus!");
return ERROR_FAIL; return ERROR_FAIL;
} }
@ -4581,11 +4580,11 @@ int riscv_interrupts_disable(struct target *target, uint64_t irq_mask, uint64_t
int riscv_interrupts_restore(struct target *target, uint64_t old_mstatus) int riscv_interrupts_restore(struct target *target, uint64_t old_mstatus)
{ {
LOG_DEBUG("Restore Interrupts"); LOG_TARGET_DEBUG(target, "Restoring interrupts.");
struct reg *reg_mstatus = register_get_by_name(target->reg_cache, struct reg *reg_mstatus = register_get_by_name(target->reg_cache,
"mstatus", true); "mstatus", true);
if (!reg_mstatus) { if (!reg_mstatus) {
LOG_ERROR("Couldn't find mstatus!"); LOG_TARGET_ERROR(target, "Couldn't find mstatus!");
return ERROR_FAIL; return ERROR_FAIL;
} }
@ -4598,17 +4597,17 @@ int riscv_interrupts_restore(struct target *target, uint64_t old_mstatus)
static int riscv_step_rtos_hart(struct target *target) static int riscv_step_rtos_hart(struct target *target)
{ {
RISCV_INFO(r); RISCV_INFO(r);
LOG_DEBUG("[%s] stepping", target_name(target)); LOG_TARGET_DEBUG(target, "Stepping.");
if (target->state != TARGET_HALTED) { if (target->state != TARGET_HALTED) {
LOG_ERROR("Hart isn't halted before single step!"); LOG_TARGET_ERROR(target, "Hart isn't halted before single step!");
return ERROR_FAIL; return ERROR_FAIL;
} }
r->on_step(target); r->on_step(target);
if (r->step_current_hart(target) != ERROR_OK) if (r->step_current_hart(target) != ERROR_OK)
return ERROR_FAIL; return ERROR_FAIL;
if (target->state != TARGET_HALTED) { if (target->state != TARGET_HALTED) {
LOG_ERROR("Hart was not halted after single step!"); LOG_TARGET_ERROR(target, "Hart was not halted after single step!");
return ERROR_FAIL; return ERROR_FAIL;
} }
return ERROR_OK; return ERROR_OK;
@ -4640,7 +4639,7 @@ static void riscv_invalidate_register_cache(struct target *target)
if (!target->reg_cache) if (!target->reg_cache)
return; return;
LOG_TARGET_DEBUG(target, "Invalidating register cache"); LOG_TARGET_DEBUG(target, "Invalidating register cache.");
register_cache_invalidate(target->reg_cache); register_cache_invalidate(target->reg_cache);
} }
@ -4886,7 +4885,7 @@ static enum riscv_halt_reason riscv_halt_reason(struct target *target)
{ {
RISCV_INFO(r); RISCV_INFO(r);
if (target->state != TARGET_HALTED) { if (target->state != TARGET_HALTED) {
LOG_ERROR("Hart is not halted!"); LOG_TARGET_ERROR(target, "Hart is not halted!");
return RISCV_HALT_UNKNOWN; return RISCV_HALT_UNKNOWN;
} }
return r->halt_reason(target); return r->halt_reason(target);
@ -4963,8 +4962,8 @@ int riscv_enumerate_triggers(struct target *target)
* implemented. There are no triggers to enumerate then and no error * implemented. There are no triggers to enumerate then and no error
* should be thrown. */ * should be thrown. */
if (result != ERROR_OK) { if (result != ERROR_OK) {
LOG_DEBUG("[%s] Cannot access tselect register. " LOG_TARGET_DEBUG(target, "Cannot access tselect register. "
"Assuming that triggers are not implemented.", target_name(target)); "Assuming that triggers are not implemented.");
r->trigger_count = 0; r->trigger_count = 0;
return ERROR_OK; return ERROR_OK;
} }
@ -5036,7 +5035,7 @@ int riscv_enumerate_triggers(struct target *target)
riscv_set_register(target, GDB_REGNO_TSELECT, tselect); riscv_set_register(target, GDB_REGNO_TSELECT, tselect);
LOG_INFO("[%s] Found %d triggers", target_name(target), r->trigger_count); LOG_TARGET_INFO(target, "Found %d triggers.", r->trigger_count);
return ERROR_OK; return ERROR_OK;
} }
@ -5259,7 +5258,7 @@ static int register_get(struct reg *reg)
buf_set_u64(reg->value, 0, reg->size, value); buf_set_u64(reg->value, 0, reg->size, value);
} }
char *str = buf_to_hex_str(reg->value, reg->size); char *str = buf_to_hex_str(reg->value, reg->size);
LOG_TARGET_DEBUG(target, "read 0x%s from %s (valid=%d)", str, reg->name, LOG_TARGET_DEBUG(target, "Read 0x%s from %s (valid=%d).", str, reg->name,
reg->valid); reg->valid);
free(str); free(str);
return ERROR_OK; return ERROR_OK;
@ -5274,7 +5273,7 @@ static int register_set(struct reg *reg, uint8_t *buf)
RISCV_INFO(r); RISCV_INFO(r);
char *str = buf_to_hex_str(buf, reg->size); char *str = buf_to_hex_str(buf, reg->size);
LOG_TARGET_DEBUG(target, "write 0x%s to %s (valid=%d)", str, reg->name, LOG_TARGET_DEBUG(target, "Write 0x%s to %s (valid=%d).", str, reg->name,
reg->valid); reg->valid);
free(str); free(str);
@ -5350,8 +5349,8 @@ int riscv_init_registers(struct target *target)
target->reg_cache->num_regs += entry->high - entry->low + 1; target->reg_cache->num_regs += entry->high - entry->low + 1;
} }
LOG_DEBUG("[%s] create register cache for %d registers", LOG_TARGET_DEBUG(target, "create register cache for %d registers",
target_name(target), target->reg_cache->num_regs); target->reg_cache->num_regs);
target->reg_cache->reg_list = target->reg_cache->reg_list =
calloc(target->reg_cache->num_regs, sizeof(struct reg)); calloc(target->reg_cache->num_regs, sizeof(struct reg));
@ -5972,7 +5971,7 @@ int riscv_init_registers(struct target *target)
r->name = entry->name; r->name = entry->name;
} }
LOG_DEBUG("Exposing additional CSR %d (name=%s)", LOG_TARGET_DEBUG(target, "Exposing additional CSR %d (name=%s).",
csr_number, entry->name ? entry->name : reg_name); csr_number, entry->name ? entry->name : reg_name);
r->exist = true; r->exist = true;
@ -5982,7 +5981,7 @@ int riscv_init_registers(struct target *target)
range_list_t *entry; range_list_t *entry;
list_for_each_entry(entry, &info->hide_csr, list) list_for_each_entry(entry, &info->hide_csr, list)
if (entry->low <= csr_number && csr_number <= entry->high) { if (entry->low <= csr_number && csr_number <= entry->high) {
LOG_TARGET_DEBUG(target, "Hiding CSR %d (name=%s)", csr_number, r->name); LOG_TARGET_DEBUG(target, "Hiding CSR %d (name=%s).", csr_number, r->name);
r->hidden = true; r->hidden = true;
break; break;
} }
@ -6025,7 +6024,7 @@ int riscv_init_registers(struct target *target)
r->name = range->name; r->name = range->name;
} }
LOG_DEBUG("Exposing additional custom register %d (name=%s)", LOG_TARGET_DEBUG(target, "Exposing additional custom register %d (name=%s).",
number, range->name ? range->name : reg_name); number, range->name ? range->name : reg_name);
custom_within_range++; custom_within_range++;

22
src/target/riscv/riscv_semihosting.c
View File

@ -57,12 +57,12 @@ enum semihosting_result riscv_semihosting(struct target *target, int *retval)
{ {
struct semihosting *semihosting = target->semihosting; struct semihosting *semihosting = target->semihosting;
if (!semihosting) { if (!semihosting) {
LOG_DEBUG(" -> NONE (!semihosting)"); LOG_TARGET_DEBUG(target, " -> NONE (!semihosting)");
return SEMIHOSTING_NONE; return SEMIHOSTING_NONE;
} }
if (!semihosting->is_active) { if (!semihosting->is_active) {
LOG_DEBUG(" -> NONE (!semihosting->is_active)"); LOG_TARGET_DEBUG(target, " -> NONE (!semihosting->is_active)");
return SEMIHOSTING_NONE; return SEMIHOSTING_NONE;
} }
@ -93,7 +93,7 @@ enum semihosting_result riscv_semihosting(struct target *target, int *retval)
LOG_TARGET_DEBUG(target, "compare 0x%08x from 0x%" PRIx64 " against 0x%08x", LOG_TARGET_DEBUG(target, "compare 0x%08x from 0x%" PRIx64 " against 0x%08x",
value, address, magic[i]); value, address, magic[i]);
if (value != magic[i]) { if (value != magic[i]) {
LOG_DEBUG(" -> NONE (no magic)"); LOG_TARGET_DEBUG(target, " -> NONE (no magic)");
return SEMIHOSTING_NONE; return SEMIHOSTING_NONE;
} }
} }
@ -109,13 +109,13 @@ enum semihosting_result riscv_semihosting(struct target *target, int *retval)
result = riscv_get_register(target, &r0, GDB_REGNO_A0); result = riscv_get_register(target, &r0, GDB_REGNO_A0);
if (result != ERROR_OK) { if (result != ERROR_OK) {
LOG_DEBUG(" -> ERROR (couldn't read a0)"); LOG_TARGET_DEBUG(target, " -> ERROR (couldn't read a0)");
return SEMIHOSTING_ERROR; return SEMIHOSTING_ERROR;
} }
result = riscv_get_register(target, &r1, GDB_REGNO_A1); result = riscv_get_register(target, &r1, GDB_REGNO_A1);
if (result != ERROR_OK) { if (result != ERROR_OK) {
LOG_DEBUG(" -> ERROR (couldn't read a1)"); LOG_TARGET_DEBUG(target, " -> ERROR (couldn't read a1)");
return SEMIHOSTING_ERROR; return SEMIHOSTING_ERROR;
} }
@ -129,12 +129,12 @@ enum semihosting_result riscv_semihosting(struct target *target, int *retval)
*retval = semihosting_common(target); *retval = semihosting_common(target);
if (*retval != ERROR_OK) { if (*retval != ERROR_OK) {
LOG_ERROR("Failed semihosting operation (0x%02X)", semihosting->op); LOG_TARGET_ERROR(target, "Failed semihosting operation (0x%02X)", semihosting->op);
return SEMIHOSTING_ERROR; return SEMIHOSTING_ERROR;
} }
} else { } else {
/* Unknown operation number, not a semihosting call. */ /* Unknown operation number, not a semihosting call. */
LOG_DEBUG(" -> NONE (unknown operation number)"); LOG_TARGET_DEBUG(target, " -> NONE (unknown operation number)");
return SEMIHOSTING_NONE; return SEMIHOSTING_NONE;
} }
} }
@ -149,11 +149,11 @@ enum semihosting_result riscv_semihosting(struct target *target, int *retval)
* operation to complete. * operation to complete.
*/ */
if (semihosting->is_resumable && !semihosting->hit_fileio) { if (semihosting->is_resumable && !semihosting->hit_fileio) {
LOG_DEBUG(" -> HANDLED"); LOG_TARGET_DEBUG(target, " -> HANDLED");
return SEMIHOSTING_HANDLED; return SEMIHOSTING_HANDLED;
} }
LOG_DEBUG(" -> WAITING"); LOG_TARGET_DEBUG(target, " -> WAITING");
return SEMIHOSTING_WAITING; return SEMIHOSTING_WAITING;
} }
@ -166,7 +166,7 @@ enum semihosting_result riscv_semihosting(struct target *target, int *retval)
*/ */
static int riscv_semihosting_setup(struct target *target, int enable) static int riscv_semihosting_setup(struct target *target, int enable)
{ {
LOG_DEBUG("[%s] enable=%d", target_name(target), enable); LOG_TARGET_DEBUG(target, "enable=%d", enable);
struct semihosting *semihosting = target->semihosting; struct semihosting *semihosting = target->semihosting;
if (semihosting) if (semihosting)
@ -183,7 +183,7 @@ static int riscv_semihosting_post_result(struct target *target)
return 0; return 0;
} }
LOG_DEBUG("0x%" PRIx64, semihosting->result); LOG_TARGET_DEBUG(target, "Result: 0x%" PRIx64, semihosting->result);
riscv_set_register(target, GDB_REGNO_A0, semihosting->result); riscv_set_register(target, GDB_REGNO_A0, semihosting->result);
return 0; return 0;
} }