Alan Carvalho de Assis <acassis@gmail.com> imx31pdk.cfg reset init event
git-svn-id: svn://svn.berlios.de/openocd/trunk@1322 b42882b7-edfa-0310-969c-e2dbd0fdcd60
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oharboe
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# The IMX31PDK eval board has a single IMX31 chip
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source [find target/imx31.cfg]
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$_TARGETNAME configure -event gdb-attach { reset init }
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$_TARGETNAME configure -event reset-init { imx31pdk_init }
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proc imx31pdk_init { } {
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# This setup puts RAM at 0x80000000
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# reset the board correctly
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reset run
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reset halt
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# ========================================
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# Init CCM
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# ========================================
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mww 0x53FC0000 0x040
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mww 0x53F80000 0x074B0B7D
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sleep 100
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# ========================================
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# 399MHz - 26MHz input, PD=1,MFI=7, MFN=27, MFD=40
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# ========================================
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mww 0x53F80004 0xFF871D50
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mww 0x53F80010 0x00271C1B
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# ========================================
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# Configure CPLD on CS5
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# ========================================
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mww 0xb8002050 0x0000DCF6
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mww 0xb8002054 0x444A4541
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mww 0xb8002058 0x44443302
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# ========================================
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# SDCLK
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# ========================================
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mww 0x43FAC26C 0
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# ========================================
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# CAS
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# ========================================
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mww 0x43FAC270 0
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# ========================================
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# RAS
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# ========================================
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mww 0x43FAC274 0
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# ========================================
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# CS2 (CSD0)
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# ========================================
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mww 0x43FAC27C 0x1000
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# ========================================
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# DQM3
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# ========================================
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mww 0x43FAC284 0
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# ========================================
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# DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 (0x288..0x2DC)
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# ========================================
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mww 0x43FAC288 0
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mww 0x43FAC28C 0
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mww 0x43FAC290 0
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mww 0x43FAC294 0
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mww 0x43FAC298 0
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mww 0x43FAC29C 0
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mww 0x43FAC2A0 0
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mww 0x43FAC2A4 0
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mww 0x43FAC2A8 0
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mww 0x43FAC2AC 0
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mww 0x43FAC2B0 0
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mww 0x43FAC2B4 0
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mww 0x43FAC2B8 0
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mww 0x43FAC2BC 0
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mww 0x43FAC2C0 0
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mww 0x43FAC2C4 0
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mww 0x43FAC2C8 0
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mww 0x43FAC2CC 0
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mww 0x43FAC2D0 0
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mww 0x43FAC2D4 0
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mww 0x43FAC2D8 0
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mww 0x43FAC2DC 0
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# ========================================
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# Initialization script for 32 bit DDR on MX31 PDK
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# ========================================
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mww 0xB8001010 0x00000004
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mww 0xB8001004 0x006ac73a
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mww 0xB8001000 0x92100000
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mww 0x80000f00 0x12344321
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mww 0xB8001000 0xa2100000
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mww 0x80000000 0x12344321
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mww 0x80000000 0x12344321
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mww 0xB8001000 0xb2100000
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mwb 0x80000033 0xda
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mwb 0x81000000 0xff
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mww 0xB8001000 0x82226080
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mww 0x80000000 0xDEADBEEF
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mww 0xB8001010 0x0000000c
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}
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@ -1,4 +1,8 @@
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echo Setting up for the FreeScale iMX31 Board.\n
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echo Script to load ledtest on iMX31PDK.\n
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# Note: you need to startup openocd with "-f board/imx31pdk.cfg"
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# in order to it initialize RAM memory.
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# SETUP GDB :
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#
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# Common gdb setup for ARM CPUs
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@ -9,104 +13,8 @@ set prompt (arm-gdb)
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set endian little
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dir .
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# DEFINE MACROS :
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#
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# Create a "refresh" macro to update gdb's screens after the cpu
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# has been stopped by the other CPU or following an "monitor allstop"
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define refresh
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monitor set hbreak
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cont
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monitor clear hbreak
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end
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# CONNECT TO TARGET :
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target remote 127.0.0.1:3333
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monitor reset run
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#FIX!!!! should be reset init!
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monitor reset halt
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# iMX31 PDK board initialization commands:
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#// init_ccm
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monitor mww 0x53FC0000 0x040
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monitor mww 0x53F80000 0x074B0B7D
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#//532-133-66.5
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#//monitor mww 0x53F80004 0xFF871D58
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#//monitor mww 0x53F80010 0x0033280C
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#// 399MHz - 26MHz input, PD=1,MFI=7, MFN=27, MFD=40
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monitor mww 0x53F80004 0xFF871D50
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monitor mww 0x53F80010 0x00271C1B
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#// 208-104-52
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#//monitor mww 0x53F80004 0xFF871D48
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#//monitor mww 0x53F80010 0x04002000
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#// Configure CPLD on CS5
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monitor mww 0xb8002050 0x0000DCF6
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monitor mww 0xb8002054 0x444A4541
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monitor mww 0xb8002058 0x44443302
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#// Disable maximum drive strength for SDRAM/DDR lines by clearing DSE1 bits
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#// in SW_PAD_CTL registers
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#// SDCLK
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monitor mww 0x43FAC26C 0
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#// CAS
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monitor mww 0x43FAC270 0
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#// RAS
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monitor mww 0x43FAC274 0
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#// CS2 (CSD0)
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monitor mww 0x43FAC27C 0x1000
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#// DQM3
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monitor mww 0x43FAC284 0
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#// DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 (0x288..0x2DC)
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monitor mww 0x43FAC288 0
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monitor mww 0x43FAC28C 0
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monitor mww 0x43FAC290 0
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monitor mww 0x43FAC294 0
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monitor mww 0x43FAC298 0
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monitor mww 0x43FAC29C 0
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monitor mww 0x43FAC2A0 0
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monitor mww 0x43FAC2A4 0
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monitor mww 0x43FAC2A8 0
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monitor mww 0x43FAC2AC 0
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monitor mww 0x43FAC2B0 0
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monitor mww 0x43FAC2B4 0
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monitor mww 0x43FAC2B8 0
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monitor mww 0x43FAC2BC 0
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monitor mww 0x43FAC2C0 0
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monitor mww 0x43FAC2C4 0
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monitor mww 0x43FAC2C8 0
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monitor mww 0x43FAC2CC 0
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monitor mww 0x43FAC2D0 0
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monitor mww 0x43FAC2D4 0
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monitor mww 0x43FAC2D8 0
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monitor mww 0x43FAC2DC 0
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#// Initialization script for 32 bit DDR on MX31 PDK
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monitor mww 0xB8001010 0x00000004
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monitor mww 0xB8001004 0x006ac73a
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monitor mww 0xB8001000 0x92100000
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monitor mww 0x80000f00 0x12344321
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monitor mww 0xB8001000 0xa2100000
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monitor mww 0x80000000 0x12344321
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monitor mww 0x80000000 0x12344321
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monitor mww 0xB8001000 0xb2100000
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#monitor char 0x80000033 0xda
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monitor mwb 0x80000033 0xda
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#monitor char 0x81000000 0xff
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monitor mwb 0x81000000 0xff
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monitor mww 0xB8001000 0x82226080
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monitor mww 0x80000000 0xDEADBEEF
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monitor mww 0xB8001010 0x0000000c
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# LOAD IMAGE :
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#
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