- add missing svn props and fix incorrect line endings from last commit
git-svn-id: svn://svn.berlios.de/openocd/trunk@1321 b42882b7-edfa-0310-969c-e2dbd0fdcd60
This commit is contained in:
ntfreak
parent
2d43ea1a45
commit
9094500ba6
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@ -1,75 +1,75 @@
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# The IMX27 ADS eval board has a single IMX27 chip
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# Note: tested on IMX27ADS Board REV-2.6 and REV-2.8
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source [find target/imx27.cfg]
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$_TARGETNAME configure -event gdb-attach { reset init }
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$_TARGETNAME configure -event reset-init { imx27ads_init }
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# The IMX27 ADS board has a NOR flash on CS0
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flash_bank cfi 0xc0000000 0x00200000 2 2 0
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proc imx27ads_init { } {
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# This setup puts RAM at 0xA0000000
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# reset the board correctly
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reset run
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reset halt
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mww 0x10000000 0x20040304
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mww 0x10020000 0x00000000
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mww 0x10000004 0xDFFBFCFB
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mww 0x10020004 0xFFFFFFFF
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sleep 100
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# ========================================
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# Configure DDR on CSD0 -- initial reset
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# ========================================
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mww 0xD8001010 0x00000008
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# ========================================
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# Configure PSRAM on CS5
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# ========================================
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mww 0xd8002050 0x0000dcf6
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mww 0xd8002054 0x444a4541
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mww 0xd8002058 0x44443302
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# ========================================
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# Configure16 bit NorFlash on CS0
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# ========================================
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mww 0xd8002000 0x0000CC03
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mww 0xd8002004 0xa0330D01
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mww 0xd8002008 0x00220800
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# ========================================
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# Configure CPLD on CS4
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# ========================================
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mww 0xd8002040 0x0000DCF6
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mww 0xd8002044 0x444A4541
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mww 0xd8002048 0x44443302
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# ========================================
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# Configure DDR on CSD0 -- wait 5000 cycle
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# ========================================
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mww 0x10027828 0x55555555
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mww 0x10027830 0x55555555
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mww 0x10027834 0x55555555
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mww 0x10027838 0x00005005
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mww 0x1002783C 0x15555555
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mww 0xD8001010 0x00000004
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mww 0xD8001004 0x00795729
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mww 0xD8001000 0x92200000
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mww 0xA0000F00 0x0
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mww 0xD8001000 0xA2200000
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mww 0xA0000F00 0x0
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mww 0xA0000F00 0x0
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mww 0xD8001000 0xB2200000
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mwb 0xA0000033 0xFF
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mwb 0xA1000000 0xAA
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mww 0xD8001000 0x82228085
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}
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# The IMX27 ADS eval board has a single IMX27 chip
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# Note: tested on IMX27ADS Board REV-2.6 and REV-2.8
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source [find target/imx27.cfg]
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$_TARGETNAME configure -event gdb-attach { reset init }
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$_TARGETNAME configure -event reset-init { imx27ads_init }
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# The IMX27 ADS board has a NOR flash on CS0
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flash_bank cfi 0xc0000000 0x00200000 2 2 0
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proc imx27ads_init { } {
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# This setup puts RAM at 0xA0000000
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# reset the board correctly
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reset run
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reset halt
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mww 0x10000000 0x20040304
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mww 0x10020000 0x00000000
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mww 0x10000004 0xDFFBFCFB
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mww 0x10020004 0xFFFFFFFF
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sleep 100
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# ========================================
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# Configure DDR on CSD0 -- initial reset
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# ========================================
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mww 0xD8001010 0x00000008
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# ========================================
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# Configure PSRAM on CS5
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# ========================================
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mww 0xd8002050 0x0000dcf6
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mww 0xd8002054 0x444a4541
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mww 0xd8002058 0x44443302
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# ========================================
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# Configure16 bit NorFlash on CS0
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# ========================================
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mww 0xd8002000 0x0000CC03
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mww 0xd8002004 0xa0330D01
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mww 0xd8002008 0x00220800
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# ========================================
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# Configure CPLD on CS4
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# ========================================
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mww 0xd8002040 0x0000DCF6
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mww 0xd8002044 0x444A4541
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mww 0xd8002048 0x44443302
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# ========================================
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# Configure DDR on CSD0 -- wait 5000 cycle
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# ========================================
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mww 0x10027828 0x55555555
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mww 0x10027830 0x55555555
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mww 0x10027834 0x55555555
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mww 0x10027838 0x00005005
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mww 0x1002783C 0x15555555
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mww 0xD8001010 0x00000004
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mww 0xD8001004 0x00795729
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mww 0xD8001000 0x92200000
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mww 0xA0000F00 0x0
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mww 0xD8001000 0xA2200000
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mww 0xA0000F00 0x0
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mww 0xA0000F00 0x0
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mww 0xD8001000 0xB2200000
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mwb 0xA0000033 0xFF
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mwb 0xA1000000 0xAA
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mww 0xD8001000 0x82228085
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}
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@ -1,42 +1,42 @@
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# $Header: $
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# This will make the test program for ARM.
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PROC=arm
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TYPE=none-linux-gnueabi
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LDSCRIPT=ldscript
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PATH:=/opt/freescale/usr/local/gcc-4.1.2-glibc-2.5-nptl-3/arm-none-linux-gnueabi/bin/:$(PATH)
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CC=$(PROC)-$(TYPE)-gcc
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AS=$(PROC)-$(TYPE)-as
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AR=$(PROC)-$(TYPE)-ar
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LD=$(PROC)-$(TYPE)-ld
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NM=$(PROC)-$(TYPE)-nm
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OBJDUMP=$(PROC)-$(TYPE)-objdump
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CFLAGS= -g -c -mcpu=arm1136j-s
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all: test.elf
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# Make a little endian image:
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# In Eclipse, add the line :
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# source gdbinit
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# to : Run -> Debug... (menu) -> Commands (tab): Commands (listbox)
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# To start gdb from a window use : arm-elf-gdb --command=gdbinit
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test.elf: test.c Makefile ldscript crt0.S
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$(CC) $(CFLAGS) -o crt0.o crt0.S
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$(CC) $(CFLAGS) -o test.o test.c
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$(LD) -g -v -T$(LDSCRIPT) -o test.elf crt0.o test.o
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$(NM) test.elf
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dump:
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$(OBJDUMP) --all-headers test.elf
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dump_test:
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$(OBJDUMP) --disassemble test.elf
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dump_full:
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$(OBJDUMP) --full-contents test.elf
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clean:
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-/bin/rm -f *.o *~ test.elf
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# $Header: $
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# This will make the test program for ARM.
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PROC=arm
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TYPE=none-linux-gnueabi
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LDSCRIPT=ldscript
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PATH:=/opt/freescale/usr/local/gcc-4.1.2-glibc-2.5-nptl-3/arm-none-linux-gnueabi/bin/:$(PATH)
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CC=$(PROC)-$(TYPE)-gcc
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AS=$(PROC)-$(TYPE)-as
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AR=$(PROC)-$(TYPE)-ar
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LD=$(PROC)-$(TYPE)-ld
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NM=$(PROC)-$(TYPE)-nm
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OBJDUMP=$(PROC)-$(TYPE)-objdump
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CFLAGS= -g -c -mcpu=arm1136j-s
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all: test.elf
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# Make a little endian image:
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# In Eclipse, add the line :
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# source gdbinit
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# to : Run -> Debug... (menu) -> Commands (tab): Commands (listbox)
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# To start gdb from a window use : arm-elf-gdb --command=gdbinit
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test.elf: test.c Makefile ldscript crt0.S
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$(CC) $(CFLAGS) -o crt0.o crt0.S
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$(CC) $(CFLAGS) -o test.o test.c
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$(LD) -g -v -T$(LDSCRIPT) -o test.elf crt0.o test.o
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$(NM) test.elf
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dump:
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$(OBJDUMP) --all-headers test.elf
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dump_test:
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$(OBJDUMP) --disassemble test.elf
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dump_full:
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$(OBJDUMP) --full-contents test.elf
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clean:
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-/bin/rm -f *.o *~ test.elf
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@ -1,47 +1,47 @@
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/* Sample initialization file */
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.extern main
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.extern exit
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/* .text is used instead of .section .text so it works with arm-aout too. */
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.text
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.code 32
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.align 0
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.global _mainCRTStartup
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.global _start
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.global start
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start:
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_start:
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_mainCRTStartup:
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/* Start by setting up a stack */
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/* Set up the stack pointer to end of bss */
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ldr r3, .LC2
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mov sp, r3
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sub sl, sp, #512 /* Still assumes 512 bytes below sl */
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mov a2, #0 /* Second arg: fill value */
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mov fp, a2 /* Null frame pointer */
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mov r7, a2 /* Null frame pointer for Thumb */
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ldr a1, .LC1 /* First arg: start of memory block */
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ldr a3, .LC2 /* Second arg: end of memory block */
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sub a3, a3, a1 /* Third arg: length of block */
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mov r0, #0 /* no arguments */
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mov r1, #0 /* no argv either */
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bl main
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bl exit /* Should not return */
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/* For Thumb, constants must be after the code since only
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positive offsets are supported for PC relative addresses. */
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.align 0
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.LC1:
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.word __bss_start__
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.LC2:
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.word __bss_end__
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/* Sample initialization file */
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.extern main
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.extern exit
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/* .text is used instead of .section .text so it works with arm-aout too. */
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.text
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.code 32
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.align 0
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.global _mainCRTStartup
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.global _start
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.global start
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start:
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_start:
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_mainCRTStartup:
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/* Start by setting up a stack */
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/* Set up the stack pointer to end of bss */
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ldr r3, .LC2
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mov sp, r3
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sub sl, sp, #512 /* Still assumes 512 bytes below sl */
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mov a2, #0 /* Second arg: fill value */
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mov fp, a2 /* Null frame pointer */
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mov r7, a2 /* Null frame pointer for Thumb */
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ldr a1, .LC1 /* First arg: start of memory block */
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ldr a3, .LC2 /* Second arg: end of memory block */
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sub a3, a3, a1 /* Third arg: length of block */
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mov r0, #0 /* no arguments */
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mov r1, #0 /* no argv either */
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bl main
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bl exit /* Should not return */
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/* For Thumb, constants must be after the code since only
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positive offsets are supported for PC relative addresses. */
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.align 0
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.LC1:
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.word __bss_start__
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.LC2:
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.word __bss_end__
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@ -1,131 +1,128 @@
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echo Setting up for the FreeScale iMX31 Board.\n
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# SETUP GDB :
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#
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# Common gdb setup for ARM CPUs
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set complaints 1
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set output-radix 10
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set input-radix 10
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set prompt (arm-gdb)
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set endian little
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dir .
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# DEFINE MACROS :
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#
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# Create a "refresh" macro to update gdb's screens after the cpu
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# has been stopped by the other CPU or following an "monitor allstop"
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define refresh
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monitor set hbreak
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cont
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monitor clear hbreak
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end
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# CONNECT TO TARGET :
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target remote 127.0.0.1:3333
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monitor reset run
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#FIX!!!! should be reset init!
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monitor reset halt
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# iMX31 PDK board initialization commands:
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#// init_ccm
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monitor mww 0x53FC0000 0x040
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monitor mww 0x53F80000 0x074B0B7D
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#//532-133-66.5
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#//monitor mww 0x53F80004 0xFF871D58
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#//monitor mww 0x53F80010 0x0033280C
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#// 399MHz - 26MHz input, PD=1,MFI=7, MFN=27, MFD=40
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monitor mww 0x53F80004 0xFF871D50
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monitor mww 0x53F80010 0x00271C1B
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#// 208-104-52
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#//monitor mww 0x53F80004 0xFF871D48
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#//monitor mww 0x53F80010 0x04002000
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#// Configure CPLD on CS5
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monitor mww 0xb8002050 0x0000DCF6
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monitor mww 0xb8002054 0x444A4541
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monitor mww 0xb8002058 0x44443302
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#// Disable maximum drive strength for SDRAM/DDR lines by clearing DSE1 bits
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#// in SW_PAD_CTL registers
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#// SDCLK
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monitor mww 0x43FAC26C 0
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#// CAS
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monitor mww 0x43FAC270 0
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#// RAS
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monitor mww 0x43FAC274 0
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#// CS2 (CSD0)
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monitor mww 0x43FAC27C 0x1000
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#// DQM3
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monitor mww 0x43FAC284 0
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#// DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 (0x288..0x2DC)
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monitor mww 0x43FAC288 0
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monitor mww 0x43FAC28C 0
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monitor mww 0x43FAC290 0
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monitor mww 0x43FAC294 0
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monitor mww 0x43FAC298 0
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monitor mww 0x43FAC29C 0
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monitor mww 0x43FAC2A0 0
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monitor mww 0x43FAC2A4 0
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monitor mww 0x43FAC2A8 0
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monitor mww 0x43FAC2AC 0
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monitor mww 0x43FAC2B0 0
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monitor mww 0x43FAC2B4 0
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monitor mww 0x43FAC2B8 0
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monitor mww 0x43FAC2BC 0
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monitor mww 0x43FAC2C0 0
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monitor mww 0x43FAC2C4 0
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monitor mww 0x43FAC2C8 0
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monitor mww 0x43FAC2CC 0
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monitor mww 0x43FAC2D0 0
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monitor mww 0x43FAC2D4 0
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monitor mww 0x43FAC2D8 0
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monitor mww 0x43FAC2DC 0
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#// Initialization script for 32 bit DDR on MX31 PDK
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monitor mww 0xB8001010 0x00000004
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monitor mww 0xB8001004 0x006ac73a
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monitor mww 0xB8001000 0x92100000
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monitor mww 0x80000f00 0x12344321
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monitor mww 0xB8001000 0xa2100000
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monitor mww 0x80000000 0x12344321
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monitor mww 0x80000000 0x12344321
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monitor mww 0xB8001000 0xb2100000
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#monitor char 0x80000033 0xda
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monitor mwb 0x80000033 0xda
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#monitor char 0x81000000 0xff
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monitor mwb 0x81000000 0xff
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monitor mww 0xB8001000 0x82226080
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monitor mww 0x80000000 0xDEADBEEF
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monitor mww 0xB8001010 0x0000000c
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# LOAD IMAGE :
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#
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# Load the program executable called "u-boot"
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load test.elf
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# Load the symbols for the program.
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symbol-file test.elf
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# RUN TO MAIN :
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#
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# Set a breakpoint at main().
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#b reset
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b main
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# Run to the breakpoint.
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c
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echo Setting up for the FreeScale iMX31 Board.\n
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# SETUP GDB :
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#
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||||
# Common gdb setup for ARM CPUs
|
||||
set complaints 1
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set output-radix 10
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set input-radix 10
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set prompt (arm-gdb)
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set endian little
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dir .
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# DEFINE MACROS :
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||||
#
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# Create a "refresh" macro to update gdb's screens after the cpu
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# has been stopped by the other CPU or following an "monitor allstop"
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define refresh
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||||
monitor set hbreak
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cont
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monitor clear hbreak
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end
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|
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# CONNECT TO TARGET :
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||||
target remote 127.0.0.1:3333
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||||
monitor reset run
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||||
#FIX!!!! should be reset init!
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||||
monitor reset halt
|
||||
|
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# iMX31 PDK board initialization commands:
|
||||
|
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#// init_ccm
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||||
|
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monitor mww 0x53FC0000 0x040
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monitor mww 0x53F80000 0x074B0B7D
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#//532-133-66.5
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#//monitor mww 0x53F80004 0xFF871D58
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#//monitor mww 0x53F80010 0x0033280C
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|
||||
#// 399MHz - 26MHz input, PD=1,MFI=7, MFN=27, MFD=40
|
||||
monitor mww 0x53F80004 0xFF871D50
|
||||
monitor mww 0x53F80010 0x00271C1B
|
||||
|
||||
#// 208-104-52
|
||||
#//monitor mww 0x53F80004 0xFF871D48
|
||||
#//monitor mww 0x53F80010 0x04002000
|
||||
|
||||
#// Configure CPLD on CS5
|
||||
monitor mww 0xb8002050 0x0000DCF6
|
||||
monitor mww 0xb8002054 0x444A4541
|
||||
monitor mww 0xb8002058 0x44443302
|
||||
|
||||
#// Disable maximum drive strength for SDRAM/DDR lines by clearing DSE1 bits
|
||||
#// in SW_PAD_CTL registers
|
||||
|
||||
#// SDCLK
|
||||
monitor mww 0x43FAC26C 0
|
||||
|
||||
#// CAS
|
||||
monitor mww 0x43FAC270 0
|
||||
|
||||
#// RAS
|
||||
monitor mww 0x43FAC274 0
|
||||
|
||||
#// CS2 (CSD0)
|
||||
monitor mww 0x43FAC27C 0x1000
|
||||
|
||||
#// DQM3
|
||||
monitor mww 0x43FAC284 0
|
||||
|
||||
#// DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 (0x288..0x2DC)
|
||||
monitor mww 0x43FAC288 0
|
||||
monitor mww 0x43FAC28C 0
|
||||
monitor mww 0x43FAC290 0
|
||||
monitor mww 0x43FAC294 0
|
||||
monitor mww 0x43FAC298 0
|
||||
monitor mww 0x43FAC29C 0
|
||||
monitor mww 0x43FAC2A0 0
|
||||
monitor mww 0x43FAC2A4 0
|
||||
monitor mww 0x43FAC2A8 0
|
||||
monitor mww 0x43FAC2AC 0
|
||||
monitor mww 0x43FAC2B0 0
|
||||
monitor mww 0x43FAC2B4 0
|
||||
monitor mww 0x43FAC2B8 0
|
||||
monitor mww 0x43FAC2BC 0
|
||||
monitor mww 0x43FAC2C0 0
|
||||
monitor mww 0x43FAC2C4 0
|
||||
monitor mww 0x43FAC2C8 0
|
||||
monitor mww 0x43FAC2CC 0
|
||||
monitor mww 0x43FAC2D0 0
|
||||
monitor mww 0x43FAC2D4 0
|
||||
monitor mww 0x43FAC2D8 0
|
||||
monitor mww 0x43FAC2DC 0
|
||||
|
||||
#// Initialization script for 32 bit DDR on MX31 PDK
|
||||
monitor mww 0xB8001010 0x00000004
|
||||
monitor mww 0xB8001004 0x006ac73a
|
||||
monitor mww 0xB8001000 0x92100000
|
||||
monitor mww 0x80000f00 0x12344321
|
||||
monitor mww 0xB8001000 0xa2100000
|
||||
monitor mww 0x80000000 0x12344321
|
||||
monitor mww 0x80000000 0x12344321
|
||||
monitor mww 0xB8001000 0xb2100000
|
||||
#monitor char 0x80000033 0xda
|
||||
monitor mwb 0x80000033 0xda
|
||||
#monitor char 0x81000000 0xff
|
||||
monitor mwb 0x81000000 0xff
|
||||
monitor mww 0xB8001000 0x82226080
|
||||
monitor mww 0x80000000 0xDEADBEEF
|
||||
monitor mww 0xB8001010 0x0000000c
|
||||
|
||||
# LOAD IMAGE :
|
||||
#
|
||||
|
||||
# Load the program executable called "u-boot"
|
||||
load test.elf
|
||||
|
||||
# Load the symbols for the program.
|
||||
symbol-file test.elf
|
||||
|
||||
# RUN TO MAIN :
|
||||
#
|
||||
# Set a breakpoint at main().
|
||||
#b reset
|
||||
b main
|
||||
|
||||
# Run to the breakpoint.
|
||||
c
|
||||
|
||||
|
|
|
|||
|
|
@ -1,18 +1,18 @@
|
|||
SECTIONS
|
||||
{
|
||||
. = 0x80000100;
|
||||
.text : { *(.text) }
|
||||
.data ALIGN(0x10): { *(.data) }
|
||||
.bss ALIGN(0x10): {
|
||||
__bss_start__ = ABSOLUTE(.);
|
||||
*(.bss)
|
||||
. += 0x100;
|
||||
}
|
||||
__bss_end__ = .;
|
||||
PROVIDE (__stack = .);
|
||||
_end = .;
|
||||
.debug_info 0 : { *(.debug_info) }
|
||||
.debug_abbrev 0 : { *(.debug_abbrev) }
|
||||
.debug_line 0 : { *(.debug_line) }
|
||||
.debug_frame 0 : { *(.debug_frame) }
|
||||
}
|
||||
SECTIONS
|
||||
{
|
||||
. = 0x80000100;
|
||||
.text : { *(.text) }
|
||||
.data ALIGN(0x10): { *(.data) }
|
||||
.bss ALIGN(0x10): {
|
||||
__bss_start__ = ABSOLUTE(.);
|
||||
*(.bss)
|
||||
. += 0x100;
|
||||
}
|
||||
__bss_end__ = .;
|
||||
PROVIDE (__stack = .);
|
||||
_end = .;
|
||||
.debug_info 0 : { *(.debug_info) }
|
||||
.debug_abbrev 0 : { *(.debug_abbrev) }
|
||||
.debug_line 0 : { *(.debug_line) }
|
||||
.debug_frame 0 : { *(.debug_frame) }
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue