semihosting: add armv7m semihosting support
do_semihosting and arm_semihosting now check the core type and use the generic arm structure. Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
This commit is contained in:
Spencer Oliver
parent
9d6ede25dd
commit
8d13a46626
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@ -39,6 +39,9 @@
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#include "arm.h"
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#include "armv4_5.h"
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#include "arm7_9_common.h"
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#include "armv7m.h"
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#include "cortex_m3.h"
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#include "register.h"
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#include "arm_semihosting.h"
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#include <helper/binarybuffer.h>
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@ -62,14 +65,19 @@ static int open_modeflags[12] = {
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static int do_semihosting(struct target *target)
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{
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struct arm *armv4_5 = target_to_arm(target);
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uint32_t r0 = buf_get_u32(armv4_5->core_cache->reg_list[0].value, 0, 32);
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uint32_t r1 = buf_get_u32(armv4_5->core_cache->reg_list[1].value, 0, 32);
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uint32_t lr = buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, ARM_MODE_SVC, 14).value, 0, 32);
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uint32_t spsr = buf_get_u32(armv4_5->spsr->value, 0, 32);;
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struct arm *arm = target_to_arm(target);
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uint32_t r0 = buf_get_u32(arm->core_cache->reg_list[0].value, 0, 32);
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uint32_t r1 = buf_get_u32(arm->core_cache->reg_list[1].value, 0, 32);
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uint32_t lr, spsr;
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uint8_t params[16];
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int retval, result;
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if (is_arm7_9(target_to_arm7_9(target)))
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{
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lr = buf_get_u32(ARMV4_5_CORE_REG_MODE(arm->core_cache, ARM_MODE_SVC, 14).value, 0, 32);
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spsr = buf_get_u32(arm->spsr->value, 0, 32);;
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}
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/*
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* TODO: lots of security issues are not considered yet, such as:
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* - no validation on target provided file descriptors
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@ -105,10 +113,10 @@ static int do_semihosting(struct target *target)
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* written file */
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result = open((char *)fn, open_modeflags[m], 0644);
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}
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armv4_5->semihosting_errno = errno;
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arm->semihosting_errno = errno;
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} else {
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result = -1;
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armv4_5->semihosting_errno = EINVAL;
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arm->semihosting_errno = EINVAL;
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}
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}
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break;
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@ -120,7 +128,7 @@ static int do_semihosting(struct target *target)
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else {
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int fd = target_buffer_get_u32(target, params+0);
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result = close(fd);
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armv4_5->semihosting_errno = errno;
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arm->semihosting_errno = errno;
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}
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break;
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@ -159,7 +167,7 @@ static int do_semihosting(struct target *target)
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uint8_t *buf = malloc(l);
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if (!buf) {
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result = -1;
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armv4_5->semihosting_errno = ENOMEM;
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arm->semihosting_errno = ENOMEM;
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} else {
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retval = target_read_buffer(target, a, l, buf);
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if (retval != ERROR_OK) {
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@ -167,7 +175,7 @@ static int do_semihosting(struct target *target)
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return retval;
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}
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result = write(fd, buf, l);
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armv4_5->semihosting_errno = errno;
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arm->semihosting_errno = errno;
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if (result >= 0)
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result = l - result;
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free(buf);
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@ -186,10 +194,10 @@ static int do_semihosting(struct target *target)
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uint8_t *buf = malloc(l);
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if (!buf) {
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result = -1;
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armv4_5->semihosting_errno = ENOMEM;
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arm->semihosting_errno = ENOMEM;
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} else {
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result = read(fd, buf, l);
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armv4_5->semihosting_errno = errno;
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arm->semihosting_errno = errno;
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if (result >= 0) {
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retval = target_write_buffer(target, a, result, buf);
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if (retval != ERROR_OK) {
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@ -229,7 +237,7 @@ static int do_semihosting(struct target *target)
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int fd = target_buffer_get_u32(target, params+0);
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off_t pos = target_buffer_get_u32(target, params+4);
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result = lseek(fd, pos, SEEK_SET);
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armv4_5->semihosting_errno = errno;
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arm->semihosting_errno = errno;
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if (result == pos)
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result = 0;
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}
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@ -244,7 +252,7 @@ static int do_semihosting(struct target *target)
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struct stat buf;
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result = fstat(fd, &buf);
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if (result == -1) {
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armv4_5->semihosting_errno = errno;
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arm->semihosting_errno = errno;
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result = -1;
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break;
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}
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@ -266,10 +274,10 @@ static int do_semihosting(struct target *target)
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return retval;
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fn[l] = 0;
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result = remove((char *)fn);
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armv4_5->semihosting_errno = errno;
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arm->semihosting_errno = errno;
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} else {
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result = -1;
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armv4_5->semihosting_errno = EINVAL;
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arm->semihosting_errno = EINVAL;
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}
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}
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break;
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@ -294,10 +302,10 @@ static int do_semihosting(struct target *target)
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fn1[l1] = 0;
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fn2[l2] = 0;
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result = rename((char *)fn1, (char *)fn2);
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armv4_5->semihosting_errno = errno;
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arm->semihosting_errno = errno;
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} else {
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result = -1;
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armv4_5->semihosting_errno = EINVAL;
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arm->semihosting_errno = EINVAL;
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}
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}
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break;
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@ -307,7 +315,7 @@ static int do_semihosting(struct target *target)
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break;
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case 0x13: /* SYS_ERRNO */
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result = armv4_5->semihosting_errno;
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result = arm->semihosting_errno;
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break;
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case 0x15: /* SYS_GET_CMDLINE */
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@ -383,25 +391,37 @@ static int do_semihosting(struct target *target)
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fprintf(stderr, "semihosting: unsupported call %#x\n",
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(unsigned) r0);
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result = -1;
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armv4_5->semihosting_errno = ENOTSUP;
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arm->semihosting_errno = ENOTSUP;
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}
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/* resume execution to the original mode */
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/* return value in R0 */
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buf_set_u32(armv4_5->core_cache->reg_list[0].value, 0, 32, result);
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armv4_5->core_cache->reg_list[0].dirty = 1;
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if (is_arm7_9(target_to_arm7_9(target)))
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{
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/* return value in R0 */
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buf_set_u32(arm->core_cache->reg_list[0].value, 0, 32, result);
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arm->core_cache->reg_list[0].dirty = 1;
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/* LR --> PC */
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buf_set_u32(armv4_5->pc->value, 0, 32, lr);
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armv4_5->pc->dirty = 1;
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/* LR --> PC */
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buf_set_u32(arm->core_cache->reg_list[15].value, 0, 32, lr);
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arm->core_cache->reg_list[15].dirty = 1;
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/* saved PSR --> current PSR */
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buf_set_u32(armv4_5->cpsr->value, 0, 32, spsr);
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armv4_5->cpsr->dirty = 1;
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armv4_5->core_mode = spsr & 0x1f;
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if (spsr & 0x20)
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armv4_5->core_state = ARM_STATE_THUMB;
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/* saved PSR --> current PSR */
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buf_set_u32(arm->cpsr->value, 0, 32, spsr);
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arm->cpsr->dirty = 1;
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arm->core_mode = spsr & 0x1f;
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if (spsr & 0x20)
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arm->core_state = ARM_STATE_THUMB;
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}
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else
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{
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/* resume execution, this will be pc+2 to skip over the
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* bkpt instruction */
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/* return result in R0 */
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buf_set_u32(arm->core_cache->reg_list[0].value, 0, 32, result);
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arm->core_cache->reg_list[0].dirty = 1;
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}
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return target_resume(target, 1, 0, 0, 0);
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}
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@ -425,59 +445,89 @@ int arm_semihosting(struct target *target, int *retval)
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uint32_t pc, lr, spsr;
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struct reg *r;
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if (!arm->is_semihosting || arm->core_mode != ARM_MODE_SVC)
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if (!arm->is_semihosting)
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return 0;
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/* Check for PC == 0x00000008 or 0xffff0008: Supervisor Call vector. */
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r = arm->pc;
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pc = buf_get_u32(r->value, 0, 32);
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if (pc != 0x00000008 && pc != 0xffff0008)
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return 0;
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if (is_arm7_9(target_to_arm7_9(target)))
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{
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if (arm->core_mode != ARM_MODE_SVC)
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return 0;
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r = arm_reg_current(arm, 14);
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lr = buf_get_u32(r->value, 0, 32);
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/* Check for PC == 0x00000008 or 0xffff0008: Supervisor Call vector. */
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r = arm->pc;
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pc = buf_get_u32(r->value, 0, 32);
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if (pc != 0x00000008 && pc != 0xffff0008)
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return 0;
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/* Core-specific code should make sure SPSR is retrieved
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* when the above checks pass...
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*/
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if (!arm->spsr->valid) {
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LOG_ERROR("SPSR not valid!");
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*retval = ERROR_FAIL;
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return 1;
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r = arm_reg_current(arm, 14);
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lr = buf_get_u32(r->value, 0, 32);
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/* Core-specific code should make sure SPSR is retrieved
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* when the above checks pass...
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*/
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if (!arm->spsr->valid) {
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LOG_ERROR("SPSR not valid!");
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*retval = ERROR_FAIL;
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return 1;
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}
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spsr = buf_get_u32(arm->spsr->value, 0, 32);
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/* check instruction that triggered this trap */
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if (spsr & (1 << 5)) {
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/* was in Thumb (or ThumbEE) mode */
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uint8_t insn_buf[2];
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uint16_t insn;
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*retval = target_read_memory(target, lr-2, 2, 1, insn_buf);
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if (*retval != ERROR_OK)
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return 1;
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insn = target_buffer_get_u16(target, insn_buf);
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/* SVC 0xab */
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if (insn != 0xDFAB)
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return 0;
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} else if (spsr & (1 << 24)) {
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/* was in Jazelle mode */
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return 0;
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} else {
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/* was in ARM mode */
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uint8_t insn_buf[4];
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uint32_t insn;
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*retval = target_read_memory(target, lr-4, 4, 1, insn_buf);
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if (*retval != ERROR_OK)
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return 1;
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insn = target_buffer_get_u32(target, insn_buf);
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/* SVC 0x123456 */
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if (insn != 0xEF123456)
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return 0;
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}
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}
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spsr = buf_get_u32(arm->spsr->value, 0, 32);
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/* check instruction that triggered this trap */
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if (spsr & (1 << 5)) {
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/* was in Thumb (or ThumbEE) mode */
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uint8_t insn_buf[2];
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else if (is_armv7m(target_to_armv7m(target)))
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{
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uint16_t insn;
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*retval = target_read_memory(target, lr-2, 2, 1, insn_buf);
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if (target->debug_reason != DBG_REASON_BREAKPOINT)
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return 0;
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r = arm->pc;
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pc = buf_get_u32(r->value, 0, 32);
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pc &= ~1;
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*retval = target_read_u16(target, pc, &insn);
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if (*retval != ERROR_OK)
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return 1;
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insn = target_buffer_get_u16(target, insn_buf);
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/* SVC 0xab */
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if (insn != 0xDFAB)
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/* bkpt 0xAB */
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if (insn != 0xBEAB)
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return 0;
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} else if (spsr & (1 << 24)) {
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/* was in Jazelle mode */
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}
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else
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{
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LOG_ERROR("Unsupported semi-hosting Target");
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return 0;
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} else {
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/* was in ARM mode */
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uint8_t insn_buf[4];
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uint32_t insn;
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*retval = target_read_memory(target, lr-4, 4, 1, insn_buf);
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if (*retval != ERROR_OK)
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return 1;
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insn = target_buffer_get_u32(target, insn_buf);
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/* SVC 0x123456 */
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if (insn != 0xEF123456)
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return 0;
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}
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*retval = do_semihosting(target);
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@ -469,14 +469,15 @@ int armv7m_arch_state(struct target *target)
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sp = buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_R13].value, 0, 32);
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LOG_USER("target halted due to %s, current mode: %s %s\n"
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"xPSR: %#8.8" PRIx32 " pc: %#8.8" PRIx32 " %csp: %#8.8" PRIx32,
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"xPSR: %#8.8" PRIx32 " pc: %#8.8" PRIx32 " %csp: %#8.8" PRIx32 "%s",
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debug_reason_name(target),
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armv7m_mode_strings[armv7m->core_mode],
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armv7m_exception_string(armv7m->exception_number),
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buf_get_u32(arm->cpsr->value, 0, 32),
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buf_get_u32(arm->pc->value, 0, 32),
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(ctrl & 0x02) ? 'p' : 'm',
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sp);
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sp,
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arm->is_semihosting ? ", semihosting" : "");
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return ERROR_OK;
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}
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@ -529,6 +530,12 @@ struct reg_cache *armv7m_build_reg_cache(struct target *target)
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return cache;
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}
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int armv7m_setup_semihosting(struct target *target, int enable)
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{
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/* nothing todo for armv7m */
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return ERROR_OK;
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}
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/** Sets up target as a generic ARMv7-M core */
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int armv7m_init_arch_info(struct target *target, struct armv7m_common *armv7m)
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{
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@ -538,6 +545,7 @@ int armv7m_init_arch_info(struct target *target, struct armv7m_common *armv7m)
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arm->core_type = ARM_MODE_THREAD;
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arm->arch_info = armv7m;
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arm->setup_semihosting = armv7m_setup_semihosting;
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/* FIXME remove v7m-specific r/w core_reg functions;
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* use the generic ARM core support..
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@ -38,7 +38,7 @@
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#include "arm_disassembler.h"
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#include "register.h"
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#include "arm_opcodes.h"
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#include "arm_semihosting.h"
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/* NOTE: most of this should work fine for the Cortex-M1 and
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* Cortex-M0 cores too, although they're ARMv6-M not ARMv7-M.
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@ -495,6 +495,9 @@ static int cortex_m3_poll(struct target *target)
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if ((retval = cortex_m3_debug_entry(target)) != ERROR_OK)
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return retval;
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if (arm_semihosting(target, &retval) != 0)
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return retval;
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target_call_event_callbacks(target, TARGET_EVENT_HALTED);
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}
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if (prev_target_state == TARGET_DEBUG_RUNNING)
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