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flash/stm32l4x: introduce stm32l4_part_info.flags for devices features 

instead of adding a new member into stm32l4_part_info for every relevant
feature, .flags serves as container for the devices' features.

identified features: F_HAS_DUAL_BANK, F_USE_ALL_WRPXX, F_HAS_TZ

Change-Id: I3093e54c6509dec33043ebe6f87675198bf1967a
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/5540
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
This commit is contained in:
Tarek BOCHKATI 2020-11-03 01:07:00 +01:00 committed by Tomas Vanek
parent 03e2bc0f3b
commit 88fa831839
1 changed files with 33 additions and 39 deletions
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72
src/flash/nor/stm32l4x.c
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@ -116,6 +116,19 @@
#define FLASH_ERASE_TIMEOUT 250 #define FLASH_ERASE_TIMEOUT 250
/* relevant STM32L4 flags ****************************************************/
#define F_NONE 0
/* this flag indicates if the device flash is with dual bank architecture */
#define F_HAS_DUAL_BANK BIT(0)
/* this flags is used for dual bank devices only, it indicates if the
* 4 WRPxx are usable if the device is configured in single-bank mode */
#define F_USE_ALL_WRPXX BIT(1)
/* this flag indicates if the device embeds a TrustZone security feature */
#define F_HAS_TZ BIT(2)
/* end of STM32L4 flags ******************************************************/
enum stm32l4_flash_reg_index { enum stm32l4_flash_reg_index {
STM32_FLASH_ACR_INDEX, STM32_FLASH_ACR_INDEX,
STM32_FLASH_KEYR_INDEX, STM32_FLASH_KEYR_INDEX,
@ -167,10 +180,7 @@ struct stm32l4_part_info {
const struct stm32l4_rev *revs; const struct stm32l4_rev *revs;
const size_t num_revs; const size_t num_revs;
const uint16_t max_flash_size_kb; const uint16_t max_flash_size_kb;
const bool has_dual_bank; const uint32_t flags; /* one bit per feature, see STM32L4 flags: macros F_XXX */
/* this field is used for dual bank devices only, it indicates if the
* 4 WRPxx are usable if the device is configured in single-bank mode */
const bool use_all_wrpxx;
const uint32_t flash_regs_base; const uint32_t flash_regs_base;
const uint32_t *default_flash_regs; const uint32_t *default_flash_regs;
const uint32_t fsize_addr; const uint32_t fsize_addr;
@ -280,8 +290,7 @@ static const struct stm32l4_part_info stm32l4_parts[] = {
.num_revs = ARRAY_SIZE(stm32_415_revs), .num_revs = ARRAY_SIZE(stm32_415_revs),
.device_str = "STM32L47/L48xx", .device_str = "STM32L47/L48xx",
.max_flash_size_kb = 1024, .max_flash_size_kb = 1024,
.has_dual_bank = true, .flags = F_HAS_DUAL_BANK,
.use_all_wrpxx = false,
.flash_regs_base = 0x40022000, .flash_regs_base = 0x40022000,
.default_flash_regs = stm32l4_flash_regs, .default_flash_regs = stm32l4_flash_regs,
.fsize_addr = 0x1FFF75E0, .fsize_addr = 0x1FFF75E0,
@ -294,8 +303,7 @@ static const struct stm32l4_part_info stm32l4_parts[] = {
.num_revs = ARRAY_SIZE(stm32_435_revs), .num_revs = ARRAY_SIZE(stm32_435_revs),
.device_str = "STM32L43/L44xx", .device_str = "STM32L43/L44xx",
.max_flash_size_kb = 256, .max_flash_size_kb = 256,
.has_dual_bank = false, .flags = F_NONE,
.use_all_wrpxx = false,
.flash_regs_base = 0x40022000, .flash_regs_base = 0x40022000,
.default_flash_regs = stm32l4_flash_regs, .default_flash_regs = stm32l4_flash_regs,
.fsize_addr = 0x1FFF75E0, .fsize_addr = 0x1FFF75E0,
@ -308,8 +316,7 @@ static const struct stm32l4_part_info stm32l4_parts[] = {
.num_revs = ARRAY_SIZE(stm32_460_revs), .num_revs = ARRAY_SIZE(stm32_460_revs),
.device_str = "STM32G07/G08xx", .device_str = "STM32G07/G08xx",
.max_flash_size_kb = 128, .max_flash_size_kb = 128,
.has_dual_bank = false, .flags = F_NONE,
.use_all_wrpxx = false,
.flash_regs_base = 0x40022000, .flash_regs_base = 0x40022000,
.default_flash_regs = stm32l4_flash_regs, .default_flash_regs = stm32l4_flash_regs,
.fsize_addr = 0x1FFF75E0, .fsize_addr = 0x1FFF75E0,
@ -322,8 +329,7 @@ static const struct stm32l4_part_info stm32l4_parts[] = {
.num_revs = ARRAY_SIZE(stm32_461_revs), .num_revs = ARRAY_SIZE(stm32_461_revs),
.device_str = "STM32L49/L4Axx", .device_str = "STM32L49/L4Axx",
.max_flash_size_kb = 1024, .max_flash_size_kb = 1024,
.has_dual_bank = true, .flags = F_HAS_DUAL_BANK,
.use_all_wrpxx = false,
.flash_regs_base = 0x40022000, .flash_regs_base = 0x40022000,
.default_flash_regs = stm32l4_flash_regs, .default_flash_regs = stm32l4_flash_regs,
.fsize_addr = 0x1FFF75E0, .fsize_addr = 0x1FFF75E0,
@ -336,8 +342,7 @@ static const struct stm32l4_part_info stm32l4_parts[] = {
.num_revs = ARRAY_SIZE(stm32_462_revs), .num_revs = ARRAY_SIZE(stm32_462_revs),
.device_str = "STM32L45/L46xx", .device_str = "STM32L45/L46xx",
.max_flash_size_kb = 512, .max_flash_size_kb = 512,
.has_dual_bank = false, .flags = F_NONE,
.use_all_wrpxx = false,
.flash_regs_base = 0x40022000, .flash_regs_base = 0x40022000,
.default_flash_regs = stm32l4_flash_regs, .default_flash_regs = stm32l4_flash_regs,
.fsize_addr = 0x1FFF75E0, .fsize_addr = 0x1FFF75E0,
@ -350,8 +355,7 @@ static const struct stm32l4_part_info stm32l4_parts[] = {
.num_revs = ARRAY_SIZE(stm32_464_revs), .num_revs = ARRAY_SIZE(stm32_464_revs),
.device_str = "STM32L41/L42xx", .device_str = "STM32L41/L42xx",
.max_flash_size_kb = 128, .max_flash_size_kb = 128,
.has_dual_bank = false, .flags = F_NONE,
.use_all_wrpxx = false,
.flash_regs_base = 0x40022000, .flash_regs_base = 0x40022000,
.default_flash_regs = stm32l4_flash_regs, .default_flash_regs = stm32l4_flash_regs,
.fsize_addr = 0x1FFF75E0, .fsize_addr = 0x1FFF75E0,
@ -364,8 +368,7 @@ static const struct stm32l4_part_info stm32l4_parts[] = {
.num_revs = ARRAY_SIZE(stm32_466_revs), .num_revs = ARRAY_SIZE(stm32_466_revs),
.device_str = "STM32G03/G04xx", .device_str = "STM32G03/G04xx",
.max_flash_size_kb = 64, .max_flash_size_kb = 64,
.has_dual_bank = false, .flags = F_NONE,
.use_all_wrpxx = false,
.flash_regs_base = 0x40022000, .flash_regs_base = 0x40022000,
.default_flash_regs = stm32l4_flash_regs, .default_flash_regs = stm32l4_flash_regs,
.fsize_addr = 0x1FFF75E0, .fsize_addr = 0x1FFF75E0,
@ -378,8 +381,7 @@ static const struct stm32l4_part_info stm32l4_parts[] = {
.num_revs = ARRAY_SIZE(stm32_468_revs), .num_revs = ARRAY_SIZE(stm32_468_revs),
.device_str = "STM32G43/G44xx", .device_str = "STM32G43/G44xx",
.max_flash_size_kb = 128, .max_flash_size_kb = 128,
.has_dual_bank = false, .flags = F_NONE,
.use_all_wrpxx = false,
.flash_regs_base = 0x40022000, .flash_regs_base = 0x40022000,
.default_flash_regs = stm32l4_flash_regs, .default_flash_regs = stm32l4_flash_regs,
.fsize_addr = 0x1FFF75E0, .fsize_addr = 0x1FFF75E0,
@ -392,8 +394,7 @@ static const struct stm32l4_part_info stm32l4_parts[] = {
.num_revs = ARRAY_SIZE(stm32_469_revs), .num_revs = ARRAY_SIZE(stm32_469_revs),
.device_str = "STM32G47/G48xx", .device_str = "STM32G47/G48xx",
.max_flash_size_kb = 512, .max_flash_size_kb = 512,
.has_dual_bank = true, .flags = F_HAS_DUAL_BANK | F_USE_ALL_WRPXX,
.use_all_wrpxx = true,
.flash_regs_base = 0x40022000, .flash_regs_base = 0x40022000,
.default_flash_regs = stm32l4_flash_regs, .default_flash_regs = stm32l4_flash_regs,
.fsize_addr = 0x1FFF75E0, .fsize_addr = 0x1FFF75E0,
@ -406,8 +407,7 @@ static const struct stm32l4_part_info stm32l4_parts[] = {
.num_revs = ARRAY_SIZE(stm32_470_revs), .num_revs = ARRAY_SIZE(stm32_470_revs),
.device_str = "STM32L4R/L4Sxx", .device_str = "STM32L4R/L4Sxx",
.max_flash_size_kb = 2048, .max_flash_size_kb = 2048,
.has_dual_bank = true, .flags = F_HAS_DUAL_BANK | F_USE_ALL_WRPXX,
.use_all_wrpxx = true,
.flash_regs_base = 0x40022000, .flash_regs_base = 0x40022000,
.default_flash_regs = stm32l4_flash_regs, .default_flash_regs = stm32l4_flash_regs,
.fsize_addr = 0x1FFF75E0, .fsize_addr = 0x1FFF75E0,
@ -420,8 +420,7 @@ static const struct stm32l4_part_info stm32l4_parts[] = {
.num_revs = ARRAY_SIZE(stm32_471_revs), .num_revs = ARRAY_SIZE(stm32_471_revs),
.device_str = "STM32L4P5/L4Q5x", .device_str = "STM32L4P5/L4Q5x",
.max_flash_size_kb = 1024, .max_flash_size_kb = 1024,
.has_dual_bank = true, .flags = F_HAS_DUAL_BANK | F_USE_ALL_WRPXX,
.use_all_wrpxx = true,
.flash_regs_base = 0x40022000, .flash_regs_base = 0x40022000,
.default_flash_regs = stm32l4_flash_regs, .default_flash_regs = stm32l4_flash_regs,
.fsize_addr = 0x1FFF75E0, .fsize_addr = 0x1FFF75E0,
@ -434,8 +433,7 @@ static const struct stm32l4_part_info stm32l4_parts[] = {
.num_revs = ARRAY_SIZE(stm32_472_revs), .num_revs = ARRAY_SIZE(stm32_472_revs),
.device_str = "STM32L55/L56xx", .device_str = "STM32L55/L56xx",
.max_flash_size_kb = 512, .max_flash_size_kb = 512,
.has_dual_bank = true, .flags = F_HAS_DUAL_BANK | F_USE_ALL_WRPXX | F_HAS_TZ,
.use_all_wrpxx = true,
.flash_regs_base = 0x40022000, .flash_regs_base = 0x40022000,
.default_flash_regs = stm32l5_ns_flash_regs, .default_flash_regs = stm32l5_ns_flash_regs,
.fsize_addr = 0x0BFA05E0, .fsize_addr = 0x0BFA05E0,
@ -448,8 +446,7 @@ static const struct stm32l4_part_info stm32l4_parts[] = {
.num_revs = ARRAY_SIZE(stm32_479_revs), .num_revs = ARRAY_SIZE(stm32_479_revs),
.device_str = "STM32G49/G4Axx", .device_str = "STM32G49/G4Axx",
.max_flash_size_kb = 512, .max_flash_size_kb = 512,
.has_dual_bank = false, .flags = F_NONE,
.use_all_wrpxx = false,
.flash_regs_base = 0x40022000, .flash_regs_base = 0x40022000,
.default_flash_regs = stm32l4_flash_regs, .default_flash_regs = stm32l4_flash_regs,
.fsize_addr = 0x1FFF75E0, .fsize_addr = 0x1FFF75E0,
@ -462,8 +459,7 @@ static const struct stm32l4_part_info stm32l4_parts[] = {
.num_revs = ARRAY_SIZE(stm32_495_revs), .num_revs = ARRAY_SIZE(stm32_495_revs),
.device_str = "STM32WB5x", .device_str = "STM32WB5x",
.max_flash_size_kb = 1024, .max_flash_size_kb = 1024,
.has_dual_bank = false, .flags = F_NONE,
.use_all_wrpxx = false,
.flash_regs_base = 0x58004000, .flash_regs_base = 0x58004000,
.default_flash_regs = stm32l4_flash_regs, .default_flash_regs = stm32l4_flash_regs,
.fsize_addr = 0x1FFF75E0, .fsize_addr = 0x1FFF75E0,
@ -476,8 +472,7 @@ static const struct stm32l4_part_info stm32l4_parts[] = {
.num_revs = ARRAY_SIZE(stm32_496_revs), .num_revs = ARRAY_SIZE(stm32_496_revs),
.device_str = "STM32WB3x", .device_str = "STM32WB3x",
.max_flash_size_kb = 512, .max_flash_size_kb = 512,
.has_dual_bank = false, .flags = F_NONE,
.use_all_wrpxx = false,
.flash_regs_base = 0x58004000, .flash_regs_base = 0x58004000,
.default_flash_regs = stm32l4_flash_regs, .default_flash_regs = stm32l4_flash_regs,
.fsize_addr = 0x1FFF75E0, .fsize_addr = 0x1FFF75E0,
@ -490,8 +485,7 @@ static const struct stm32l4_part_info stm32l4_parts[] = {
.num_revs = ARRAY_SIZE(stm32_497_revs), .num_revs = ARRAY_SIZE(stm32_497_revs),
.device_str = "STM32WLEx", .device_str = "STM32WLEx",
.max_flash_size_kb = 256, .max_flash_size_kb = 256,
.has_dual_bank = false, .flags = F_NONE,
.use_all_wrpxx = false,
.flash_regs_base = 0x58004000, .flash_regs_base = 0x58004000,
.default_flash_regs = stm32l4_flash_regs, .default_flash_regs = stm32l4_flash_regs,
.fsize_addr = 0x1FFF75E0, .fsize_addr = 0x1FFF75E0,
@ -847,7 +841,7 @@ static int stm32l4_get_all_wrpxy(struct flash_bank *bank, enum stm32_bank_id dev
return ret; return ret;
/* for some devices (like STM32L4R/S) in single-bank mode, the 4 WRPxx are usable */ /* for some devices (like STM32L4R/S) in single-bank mode, the 4 WRPxx are usable */
if (stm32l4_info->part_info->use_all_wrpxx && !stm32l4_info->dual_bank_mode) if ((stm32l4_info->part_info->flags & F_USE_ALL_WRPXX) && !stm32l4_info->dual_bank_mode)
wrp2y_sectors_offset = 0; wrp2y_sectors_offset = 0;
} }
@ -1611,7 +1605,7 @@ static int stm32l4_mass_erase(struct flash_bank *bank)
uint32_t action = FLASH_MER1; uint32_t action = FLASH_MER1;
if (stm32l4_info->part_info->has_dual_bank) if (stm32l4_info->part_info->flags & F_HAS_DUAL_BANK)
action |= FLASH_MER2; action |= FLASH_MER2;
if (target->state != TARGET_HALTED) { if (target->state != TARGET_HALTED) {
@ -1858,7 +1852,7 @@ COMMAND_HANDLER(stm32l4_handle_wrp_info_command)
} }
if (dev_bank_id == STM32_BANK2) { if (dev_bank_id == STM32_BANK2) {
if (!stm32l4_info->part_info->has_dual_bank) { if (!(stm32l4_info->part_info->flags & F_HAS_DUAL_BANK)) {
LOG_ERROR("this device has no second bank"); LOG_ERROR("this device has no second bank");
return ERROR_FAIL; return ERROR_FAIL;
} else if (!stm32l4_info->dual_bank_mode) { } else if (!stm32l4_info->dual_bank_mode) {