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ARM: switch target_to_armv4_5() to target_to_arm() 

And remove that old symbol.

Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
This commit is contained in:
David Brownell 2009-12-04 19:43:03 -08:00
parent 56e0171420
commit 87589043fa
8 changed files with 18 additions and 20 deletions
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2
src/target/arm7tdmi.c
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@ -641,7 +641,7 @@ static void arm7tdmi_branch_resume_thumb(struct target *target)
static void arm7tdmi_build_reg_cache(struct target *target) static void arm7tdmi_build_reg_cache(struct target *target)
{ {
struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache); struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
struct arm *armv4_5 = target_to_armv4_5(target); struct arm *armv4_5 = target_to_arm(target);
(*cache_p) = armv4_5_build_reg_cache(target, armv4_5); (*cache_p) = armv4_5_build_reg_cache(target, armv4_5);
} }

4
src/target/arm920t.c
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@ -212,7 +212,7 @@ static int arm920t_execute_cp15(struct target *target, uint32_t cp15_opcode,
static int arm920t_read_cp15_interpreted(struct target *target, static int arm920t_read_cp15_interpreted(struct target *target,
uint32_t cp15_opcode, uint32_t address, uint32_t *value) uint32_t cp15_opcode, uint32_t address, uint32_t *value)
{ {
struct arm *armv4_5 = target_to_armv4_5(target); struct arm *armv4_5 = target_to_arm(target);
uint32_t* regs_p[1]; uint32_t* regs_p[1];
uint32_t regs[2]; uint32_t regs[2];
uint32_t cp15c15 = 0x0; uint32_t cp15c15 = 0x0;
@ -259,7 +259,7 @@ int arm920t_write_cp15_interpreted(struct target *target,
uint32_t cp15_opcode, uint32_t value, uint32_t address) uint32_t cp15_opcode, uint32_t value, uint32_t address)
{ {
uint32_t cp15c15 = 0x0; uint32_t cp15c15 = 0x0;
struct arm *armv4_5 = target_to_armv4_5(target); struct arm *armv4_5 = target_to_arm(target);
uint32_t regs[2]; uint32_t regs[2];
struct reg *r = armv4_5->core_cache->reg_list; struct reg *r = armv4_5->core_cache->reg_list;

2
src/target/arm9tdmi.c
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@ -751,7 +751,7 @@ void arm9tdmi_disable_single_step(struct target *target)
static void arm9tdmi_build_reg_cache(struct target *target) static void arm9tdmi_build_reg_cache(struct target *target)
{ {
struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache); struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
struct arm *armv4_5 = target_to_armv4_5(target); struct arm *armv4_5 = target_to_arm(target);
(*cache_p) = armv4_5_build_reg_cache(target, armv4_5); (*cache_p) = armv4_5_build_reg_cache(target, armv4_5);
} }

4
src/target/arm_semihosting.c
View File

@ -43,7 +43,7 @@
static int do_semihosting(struct target *target) static int do_semihosting(struct target *target)
{ {
struct arm *armv4_5 = target_to_armv4_5(target); struct arm *armv4_5 = target_to_arm(target);
uint32_t r0 = buf_get_u32(armv4_5->core_cache->reg_list[0].value, 0, 32); uint32_t r0 = buf_get_u32(armv4_5->core_cache->reg_list[0].value, 0, 32);
uint32_t r1 = buf_get_u32(armv4_5->core_cache->reg_list[1].value, 0, 32); uint32_t r1 = buf_get_u32(armv4_5->core_cache->reg_list[1].value, 0, 32);
uint32_t lr = buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, ARM_MODE_SVC, 14).value, 0, 32); uint32_t lr = buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, ARM_MODE_SVC, 14).value, 0, 32);
@ -406,7 +406,7 @@ static int do_semihosting(struct target *target)
*/ */
int arm_semihosting(struct target *target, int *retval) int arm_semihosting(struct target *target, int *retval)
{ {
struct arm *arm = target_to_armv4_5(target); struct arm *arm = target_to_arm(target);
uint32_t lr, spsr; uint32_t lr, spsr;
struct reg *r; struct reg *r;

2
src/target/arm_simulator.c
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@ -850,7 +850,7 @@ static enum arm_mode armv4_5_get_mode(struct arm_sim_interface *sim)
int arm_simulate_step(struct target *target, uint32_t *dry_run_pc) int arm_simulate_step(struct target *target, uint32_t *dry_run_pc)
{ {
struct arm *armv4_5 = target_to_armv4_5(target); struct arm *armv4_5 = target_to_arm(target);
struct arm_sim_interface sim; struct arm_sim_interface sim;
sim.user_data = armv4_5; sim.user_data = armv4_5;

16
src/target/armv4_5.c
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@ -491,7 +491,7 @@ static int armv4_5_set_core_reg(struct reg *reg, uint8_t *buf)
{ {
struct arm_reg *armv4_5 = reg->arch_info; struct arm_reg *armv4_5 = reg->arch_info;
struct target *target = armv4_5->target; struct target *target = armv4_5->target;
struct arm *armv4_5_target = target_to_armv4_5(target); struct arm *armv4_5_target = target_to_arm(target);
uint32_t value = buf_get_u32(buf, 0, 32); uint32_t value = buf_get_u32(buf, 0, 32);
if (target->state != TARGET_HALTED) if (target->state != TARGET_HALTED)
@ -583,7 +583,7 @@ struct reg_cache* armv4_5_build_reg_cache(struct target *target, struct arm *arm
int armv4_5_arch_state(struct target *target) int armv4_5_arch_state(struct target *target)
{ {
struct arm *armv4_5 = target_to_armv4_5(target); struct arm *armv4_5 = target_to_arm(target);
if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC) if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
{ {
@ -611,7 +611,7 @@ int armv4_5_arch_state(struct target *target)
COMMAND_HANDLER(handle_armv4_5_reg_command) COMMAND_HANDLER(handle_armv4_5_reg_command)
{ {
struct target *target = get_current_target(CMD_CTX); struct target *target = get_current_target(CMD_CTX);
struct arm *armv4_5 = target_to_armv4_5(target); struct arm *armv4_5 = target_to_arm(target);
unsigned num_regs; unsigned num_regs;
struct reg *regs; struct reg *regs;
@ -698,7 +698,7 @@ COMMAND_HANDLER(handle_armv4_5_reg_command)
COMMAND_HANDLER(handle_armv4_5_core_state_command) COMMAND_HANDLER(handle_armv4_5_core_state_command)
{ {
struct target *target = get_current_target(CMD_CTX); struct target *target = get_current_target(CMD_CTX);
struct arm *armv4_5 = target_to_armv4_5(target); struct arm *armv4_5 = target_to_arm(target);
if (!is_arm(armv4_5)) if (!is_arm(armv4_5))
{ {
@ -974,7 +974,7 @@ const struct command_registration arm_command_handlers[] = {
int armv4_5_get_gdb_reg_list(struct target *target, struct reg **reg_list[], int *reg_list_size) int armv4_5_get_gdb_reg_list(struct target *target, struct reg **reg_list[], int *reg_list_size)
{ {
struct arm *armv4_5 = target_to_armv4_5(target); struct arm *armv4_5 = target_to_arm(target);
int i; int i;
if (!is_arm_mode(armv4_5->core_mode)) if (!is_arm_mode(armv4_5->core_mode))
@ -999,7 +999,7 @@ int armv4_5_get_gdb_reg_list(struct target *target, struct reg **reg_list[], int
static int armv4_5_run_algorithm_completion(struct target *target, uint32_t exit_point, int timeout_ms, void *arch_info) static int armv4_5_run_algorithm_completion(struct target *target, uint32_t exit_point, int timeout_ms, void *arch_info)
{ {
int retval; int retval;
struct arm *armv4_5 = target_to_armv4_5(target); struct arm *armv4_5 = target_to_arm(target);
if ((retval = target_wait_state(target, TARGET_HALTED, timeout_ms)) != ERROR_OK) if ((retval = target_wait_state(target, TARGET_HALTED, timeout_ms)) != ERROR_OK)
{ {
@ -1036,7 +1036,7 @@ int armv4_5_run_algorithm_inner(struct target *target,
int (*run_it)(struct target *target, uint32_t exit_point, int (*run_it)(struct target *target, uint32_t exit_point,
int timeout_ms, void *arch_info)) int timeout_ms, void *arch_info))
{ {
struct arm *armv4_5 = target_to_armv4_5(target); struct arm *armv4_5 = target_to_arm(target);
struct armv4_5_algorithm *armv4_5_algorithm_info = arch_info; struct armv4_5_algorithm *armv4_5_algorithm_info = arch_info;
enum arm_state core_state = armv4_5->core_state; enum arm_state core_state = armv4_5->core_state;
uint32_t context[17]; uint32_t context[17];
@ -1388,7 +1388,7 @@ int arm_blank_check_memory(struct target *target,
static int arm_full_context(struct target *target) static int arm_full_context(struct target *target)
{ {
struct arm *armv4_5 = target_to_armv4_5(target); struct arm *armv4_5 = target_to_arm(target);
unsigned num_regs = armv4_5->core_cache->num_regs; unsigned num_regs = armv4_5->core_cache->num_regs;
struct reg *reg = armv4_5->core_cache->reg_list; struct reg *reg = armv4_5->core_cache->reg_list;
int retval = ERROR_OK; int retval = ERROR_OK;

2
src/target/armv4_5.h
View File

@ -141,8 +141,6 @@ struct arm
void *arch_info; void *arch_info;
}; };
#define target_to_armv4_5 target_to_arm
/** Convert target handle to generic ARM target state handle. */ /** Convert target handle to generic ARM target state handle. */
static inline struct arm *target_to_arm(struct target *target) static inline struct arm *target_to_arm(struct target *target)
{ {

6
src/target/xscale.c
View File

@ -1429,7 +1429,7 @@ static int xscale_step_inner(struct target *target, int current,
static int xscale_step(struct target *target, int current, static int xscale_step(struct target *target, int current,
uint32_t address, int handle_breakpoints) uint32_t address, int handle_breakpoints)
{ {
struct arm *armv4_5 = target_to_armv4_5(target); struct arm *armv4_5 = target_to_arm(target);
struct breakpoint *breakpoint = target->breakpoints; struct breakpoint *breakpoint = target->breakpoints;
uint32_t current_pc; uint32_t current_pc;
@ -1675,7 +1675,7 @@ static int xscale_write_core_reg(struct target *target, struct reg *r,
static int xscale_full_context(struct target *target) static int xscale_full_context(struct target *target)
{ {
struct arm *armv4_5 = target_to_armv4_5(target); struct arm *armv4_5 = target_to_arm(target);
uint32_t *buffer; uint32_t *buffer;
@ -1757,7 +1757,7 @@ static int xscale_full_context(struct target *target)
static int xscale_restore_banked(struct target *target) static int xscale_restore_banked(struct target *target)
{ {
struct arm *armv4_5 = target_to_armv4_5(target); struct arm *armv4_5 = target_to_arm(target);
int i, j; int i, j;