ARM: rename armv4_5_state_* as arm_state_*
And make arm_state_strings[] be const. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
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@ -237,7 +237,7 @@ static int arm720t_arch_state(struct target *target)
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LOG_USER("target halted in %s state due to %s, current mode: %s\n"
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"cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "\n"
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"MMU: %s, Cache: %s",
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armv4_5_state_strings[armv4_5->core_state],
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arm_state_strings[armv4_5->core_state],
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Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name ,
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arm_mode_name(armv4_5->core_mode),
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buf_get_u32(armv4_5->cpsr->value, 0, 32),
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@ -451,7 +451,7 @@ int arm920t_arch_state(struct target *target)
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LOG_USER("target halted in %s state due to %s, current mode: %s\n"
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"cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "\n"
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"MMU: %s, D-Cache: %s, I-Cache: %s",
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armv4_5_state_strings[armv4_5->core_state],
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arm_state_strings[armv4_5->core_state],
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Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name,
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arm_mode_name(armv4_5->core_mode),
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buf_get_u32(armv4_5->cpsr->value, 0, 32),
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@ -507,7 +507,7 @@ int arm926ejs_arch_state(struct target *target)
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LOG_USER("target halted in %s state due to %s, current mode: %s\n"
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"cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "\n"
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"MMU: %s, D-Cache: %s, I-Cache: %s",
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armv4_5_state_strings[armv4_5->core_state],
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arm_state_strings[armv4_5->core_state],
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Jim_Nvp_value2name_simple(nvp_target_debug_reason,target->debug_reason)->name,
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arm_mode_name(armv4_5->core_mode),
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buf_get_u32(armv4_5->cpsr->value, 0, 32),
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@ -824,14 +824,14 @@ static uint32_t armv4_5_get_cpsr(struct arm_sim_interface *sim, int pos, int bit
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return buf_get_u32(armv4_5->cpsr->value, pos, bits);
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}
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static enum armv4_5_state armv4_5_get_state(struct arm_sim_interface *sim)
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static enum arm_state armv4_5_get_state(struct arm_sim_interface *sim)
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{
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struct arm *armv4_5 = (struct arm *)sim->user_data;
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return armv4_5->core_state;
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}
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static void armv4_5_set_state(struct arm_sim_interface *sim, enum armv4_5_state mode)
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static void armv4_5_set_state(struct arm_sim_interface *sim, enum arm_state mode)
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{
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struct arm *armv4_5 = (struct arm *)sim->user_data;
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@ -32,8 +32,8 @@ struct arm_sim_interface
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uint32_t (*get_reg_mode)(struct arm_sim_interface *sim, int reg);
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void (*set_reg_mode)(struct arm_sim_interface *sim, int reg, uint32_t value);
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uint32_t (*get_cpsr)(struct arm_sim_interface *sim, int pos, int bits);
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enum armv4_5_state (*get_state)(struct arm_sim_interface *sim);
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void (*set_state)(struct arm_sim_interface *sim, enum armv4_5_state mode);
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enum arm_state (*get_state)(struct arm_sim_interface *sim);
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void (*set_state)(struct arm_sim_interface *sim, enum arm_state mode);
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enum arm_mode (*get_mode)(struct arm_sim_interface *sim);
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};
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@ -216,7 +216,7 @@ enum arm_mode armv4_5_number_to_mode(int number)
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}
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}
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char* armv4_5_state_strings[] =
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const char *arm_state_strings[] =
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{
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"ARM", "Thumb", "Jazelle", "ThumbEE",
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};
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@ -374,7 +374,7 @@ void arm_set_cpsr(struct arm *arm, uint32_t cpsr)
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: arm->core_cache->reg_list + arm->map[16];
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/* Older ARMs won't have the J bit */
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enum armv4_5_state state;
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enum arm_state state;
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if (cpsr & (1 << 5)) { /* T */
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if (cpsr & (1 << 24)) { /* J */
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@ -393,7 +393,7 @@ void arm_set_cpsr(struct arm *arm, uint32_t cpsr)
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LOG_DEBUG("set CPSR %#8.8x: %s mode, %s state", (unsigned) cpsr,
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arm_mode_name(mode),
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armv4_5_state_strings[arm->core_state]);
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arm_state_strings[arm->core_state]);
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}
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/**
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@ -593,7 +593,7 @@ int armv4_5_arch_state(struct target *target)
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LOG_USER("target halted in %s state due to %s, current mode: %s\n"
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"cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "%s",
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armv4_5_state_strings[armv4_5->core_state],
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arm_state_strings[armv4_5->core_state],
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Jim_Nvp_value2name_simple(nvp_target_debug_reason,
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target->debug_reason)->name,
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arm_mode_name(armv4_5->core_mode),
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@ -718,7 +718,7 @@ COMMAND_HANDLER(handle_armv4_5_core_state_command)
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}
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}
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command_print(CMD_CTX, "core state: %s", armv4_5_state_strings[armv4_5->core_state]);
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command_print(CMD_CTX, "core state: %s", arm_state_strings[armv4_5->core_state]);
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return ERROR_OK;
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}
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@ -1038,7 +1038,7 @@ int armv4_5_run_algorithm_inner(struct target *target,
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{
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struct arm *armv4_5 = target_to_armv4_5(target);
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struct armv4_5_algorithm *armv4_5_algorithm_info = arch_info;
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enum armv4_5_state core_state = armv4_5->core_state;
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enum arm_state core_state = armv4_5->core_state;
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uint32_t context[17];
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uint32_t cpsr;
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int exit_breakpoint_size = 0;
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@ -49,15 +49,15 @@ bool is_arm_mode(unsigned psr_mode);
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int arm_mode_to_number(enum arm_mode mode);
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enum arm_mode armv4_5_number_to_mode(int number);
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typedef enum armv4_5_state
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typedef enum arm_state
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{
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ARM_STATE_ARM,
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ARM_STATE_THUMB,
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ARM_STATE_JAZELLE,
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ARM_STATE_THUMB_EE,
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} armv4_5_state_t;
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} arm_state_t;
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extern char* armv4_5_state_strings[];
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extern const char *arm_state_strings[];
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extern const int armv4_5_core_reg_map[8][17];
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@ -98,7 +98,7 @@ struct arm
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enum arm_mode core_type;
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enum arm_mode core_mode;
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enum armv4_5_state core_state;
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enum arm_state core_state;
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/** Flag reporting unavailability of the BKPT instruction. */
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bool is_armv4;
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@ -159,7 +159,7 @@ struct armv4_5_algorithm
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int common_magic;
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enum arm_mode core_mode;
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enum armv4_5_state core_state;
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enum arm_state core_state;
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};
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struct arm_reg
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@ -119,7 +119,7 @@ struct armv7a_algorithm
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int common_magic;
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enum arm_mode core_mode;
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enum armv4_5_state core_state;
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enum arm_state core_state;
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};
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struct armv7a_core_reg
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@ -164,7 +164,7 @@ struct etm_context
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uint32_t trace_depth; /* number of cycles to be analyzed, 0 if no data available */
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etm_portmode_t portmode; /* normal, multiplexed or demultiplexed */
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etmv1_tracemode_t tracemode; /* type of info trace contains */
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int /*armv4_5_state_t*/ core_state; /* current core state */
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int /*arm_state_t*/ core_state; /* current core state */
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struct image *image; /* source for target opcodes */
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uint32_t pipe_index; /* current trace cycle */
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uint32_t data_index; /* cycle holding next data packet */
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@ -455,7 +455,7 @@ int feroceon_bulk_write_memory(struct target *target, uint32_t address, uint32_t
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int retval;
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struct arm *armv4_5 = target->arch_info;
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struct arm7_9_common *arm7_9 = armv4_5->arch_info;
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enum armv4_5_state core_state = armv4_5->core_state;
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enum arm_state core_state = armv4_5->core_state;
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uint32_t x, flip, shift, save[7];
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uint32_t i;
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@ -867,7 +867,7 @@ static int xscale_arch_state(struct target *target)
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"cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "\n"
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"MMU: %s, D-Cache: %s, I-Cache: %s"
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"%s",
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armv4_5_state_strings[armv4_5->core_state],
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arm_state_strings[armv4_5->core_state],
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Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name ,
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arm_mode_name(armv4_5->core_mode),
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buf_get_u32(armv4_5->cpsr->value, 0, 32),
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@ -79,7 +79,7 @@ struct xscale_trace
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int buffer_fill; /* maximum number of trace runs to read (-1 for wrap-around) */
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int pc_ok;
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uint32_t current_pc;
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armv4_5_state_t core_state; /* current core state (ARM, Thumb, Jazelle) */
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arm_state_t core_state; /* current core state (ARM, Thumb, Jazelle) */
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};
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struct xscale_common
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