Remove unused functionality.
Change-Id: I0c1464e2e6aa12d0cb1025ed0a7c1c483e7403b7
This commit is contained in:
parent
5d3f5c35d2
commit
85bfab36ad
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@ -21,7 +21,6 @@ int riscv_program_init(struct riscv_program *p, struct target *target)
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memset(p, 0, sizeof(*p));
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memset(p, 0, sizeof(*p));
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p->target = target;
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p->target = target;
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p->instruction_count = 0;
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p->instruction_count = 0;
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p->data_count = 0;
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p->writes_memory = 0;
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p->writes_memory = 0;
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p->target_xlen = riscv_xlen(target);
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p->target_xlen = riscv_xlen(target);
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for (size_t i = 0; i < RISCV_REGISTER_COUNT; ++i) {
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for (size_t i = 0; i < RISCV_REGISTER_COUNT; ++i) {
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@ -84,7 +83,7 @@ int riscv_program_exec(struct riscv_program *p, struct target *t)
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}
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}
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for (size_t i = 0; i < riscv_debug_buffer_size(p->target); ++i)
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for (size_t i = 0; i < riscv_debug_buffer_size(p->target); ++i)
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if (i >= riscv_debug_buffer_size(p->target) - p->data_count)
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if (i >= riscv_debug_buffer_size(p->target))
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p->debug_buffer[i] = riscv_read_debug_buffer(t, i);
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p->debug_buffer[i] = riscv_read_debug_buffer(t, i);
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for (size_t i = GDB_REGNO_XPR0; i <= GDB_REGNO_XPR31; ++i)
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for (size_t i = GDB_REGNO_XPR0; i <= GDB_REGNO_XPR31; ++i)
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@ -298,56 +297,6 @@ int riscv_program_addi(struct riscv_program *p, enum gdb_regno d, enum gdb_regno
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return riscv_program_insert(p, addi(d, s, u));
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return riscv_program_insert(p, addi(d, s, u));
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}
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}
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int riscv_program_fsx(struct riscv_program *p, enum gdb_regno d, riscv_addr_t addr)
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{
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assert(d >= GDB_REGNO_FPR0);
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assert(d <= GDB_REGNO_FPR31);
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enum gdb_regno t = riscv_program_gah(p, addr) == 0
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? GDB_REGNO_X0
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: riscv_program_gettemp(p);
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if (riscv_program_lah(p, t, addr) != ERROR_OK)
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return ERROR_FAIL;
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uint32_t instruction;
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switch (p->target->reg_cache->reg_list[GDB_REGNO_FPR0].size) {
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case 64:
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instruction = fsd(d - GDB_REGNO_FPR0, t, riscv_program_gal(p, addr));
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break;
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case 32:
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instruction = fsw(d - GDB_REGNO_FPR0, t, riscv_program_gal(p, addr));
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break;
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default:
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return ERROR_FAIL;
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}
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if (riscv_program_insert(p, instruction) != ERROR_OK)
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return ERROR_FAIL;
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riscv_program_puttemp(p, t);
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p->writes_memory = true;
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return ERROR_OK;
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}
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int riscv_program_flx(struct riscv_program *p, enum gdb_regno d, riscv_addr_t addr)
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{
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assert(d >= GDB_REGNO_FPR0);
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assert(d <= GDB_REGNO_FPR31);
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enum gdb_regno t = riscv_program_gah(p, addr) == 0 ? GDB_REGNO_X0 : d;
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if (riscv_program_lah(p, t, addr) != ERROR_OK)
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return ERROR_FAIL;
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uint32_t instruction;
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switch (p->target->reg_cache->reg_list[GDB_REGNO_FPR0].size) {
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case 64:
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instruction = fld(d - GDB_REGNO_FPR0, t, riscv_program_gal(p, addr));
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break;
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case 32:
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instruction = flw(d - GDB_REGNO_FPR0, t, riscv_program_gal(p, addr));
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break;
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default:
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return ERROR_FAIL;
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}
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if (riscv_program_insert(p, instruction) != ERROR_OK)
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return ERROR_FAIL;
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return ERROR_OK;
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}
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int riscv_program_li(struct riscv_program *p, enum gdb_regno d, riscv_reg_t c)
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int riscv_program_li(struct riscv_program *p, enum gdb_regno d, riscv_reg_t c)
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{
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{
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if (riscv_program_lui(p, d, c >> 12) != ERROR_OK)
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if (riscv_program_lui(p, d, c >> 12) != ERROR_OK)
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@ -371,13 +320,6 @@ int riscv_program_do_restore_register(struct riscv_program *p, enum gdb_regno r)
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return ERROR_OK;
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return ERROR_OK;
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}
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}
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void riscv_program_reserve_register(struct riscv_program *p, enum gdb_regno r)
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{
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assert(r < RISCV_REGISTER_COUNT);
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assert(p->in_use[r] == 0);
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p->in_use[r] = 1;
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}
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enum gdb_regno riscv_program_gettemp(struct riscv_program *p)
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enum gdb_regno riscv_program_gettemp(struct riscv_program *p)
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{
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{
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for (size_t i = GDB_REGNO_S0; i <= GDB_REGNO_XPR31; ++i) {
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for (size_t i = GDB_REGNO_S0; i <= GDB_REGNO_XPR31; ++i) {
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@ -431,10 +373,9 @@ int riscv_program_lal(struct riscv_program *p, enum gdb_regno d, riscv_addr_t ad
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int riscv_program_insert(struct riscv_program *p, riscv_insn_t i)
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int riscv_program_insert(struct riscv_program *p, riscv_insn_t i)
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{
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{
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if (p->instruction_count + p->data_count + 1 > riscv_debug_buffer_size(p->target)) {
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if (p->instruction_count >= riscv_debug_buffer_size(p->target)) {
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LOG_ERROR("Unable to insert instruction:");
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LOG_ERROR("Unable to insert instruction:");
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LOG_ERROR(" instruction_count=%d", (int)p->instruction_count);
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LOG_ERROR(" instruction_count=%d", (int)p->instruction_count);
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LOG_ERROR(" data_count =%d", (int)p->data_count);
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LOG_ERROR(" buffer size =%d", (int)riscv_debug_buffer_size(p->target));
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LOG_ERROR(" buffer size =%d", (int)riscv_debug_buffer_size(p->target));
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abort();
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abort();
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}
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}
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@ -15,11 +15,8 @@ struct riscv_program {
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uint32_t debug_buffer[RISCV_MAX_DEBUG_BUFFER_SIZE];
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uint32_t debug_buffer[RISCV_MAX_DEBUG_BUFFER_SIZE];
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/* The debug buffer is allocated in two directions: instructions go at
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/* Number of 32-bit instructions in the program. */
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* the start, while data goes at the end. When they meet in the middle
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* this blows up. */
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size_t instruction_count;
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size_t instruction_count;
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size_t data_count;
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/* Side effects of executing this program. These must be accounted for
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/* Side effects of executing this program. These must be accounted for
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* in order to maintain correct executing of the target system. */
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* in order to maintain correct executing of the target system. */
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@ -29,10 +26,6 @@ struct riscv_program {
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/* When a register is used it will be set in this array. */
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/* When a register is used it will be set in this array. */
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bool in_use[RISCV_REGISTER_COUNT];
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bool in_use[RISCV_REGISTER_COUNT];
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/* Remembers the registers that have been saved into dscratch
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* registers. These are restored */
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enum gdb_regno dscratch_saved[RISCV_DSCRATCH_COUNT];
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/* XLEN on the target. */
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/* XLEN on the target. */
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int target_xlen;
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int target_xlen;
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};
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};
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@ -101,9 +94,6 @@ int riscv_program_ebreak(struct riscv_program *p);
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int riscv_program_lui(struct riscv_program *p, enum gdb_regno d, int32_t u);
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int riscv_program_lui(struct riscv_program *p, enum gdb_regno d, int32_t u);
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int riscv_program_addi(struct riscv_program *p, enum gdb_regno d, enum gdb_regno s, int16_t i);
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int riscv_program_addi(struct riscv_program *p, enum gdb_regno d, enum gdb_regno s, int16_t i);
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int riscv_program_fsx(struct riscv_program *p, enum gdb_regno s, riscv_addr_t addr);
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int riscv_program_flx(struct riscv_program *p, enum gdb_regno d, riscv_addr_t addr);
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/* Assembler macros. */
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/* Assembler macros. */
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int riscv_program_li(struct riscv_program *p, enum gdb_regno d, riscv_reg_t c);
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int riscv_program_li(struct riscv_program *p, enum gdb_regno d, riscv_reg_t c);
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int riscv_program_la(struct riscv_program *p, enum gdb_regno d, riscv_addr_t a);
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int riscv_program_la(struct riscv_program *p, enum gdb_regno d, riscv_addr_t a);
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@ -113,7 +103,6 @@ int riscv_program_la(struct riscv_program *p, enum gdb_regno d, riscv_addr_t a);
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* reserving registers -- it's expected that this has been called as the first
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* reserving registers -- it's expected that this has been called as the first
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* thing in the program's execution to reserve registers that can't be touched
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* thing in the program's execution to reserve registers that can't be touched
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* by the program's execution. */
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* by the program's execution. */
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void riscv_program_reserve_register(struct riscv_program *p, enum gdb_regno r);
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enum gdb_regno riscv_program_gettemp(struct riscv_program *p);
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enum gdb_regno riscv_program_gettemp(struct riscv_program *p);
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void riscv_program_puttemp(struct riscv_program *p, enum gdb_regno r);
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void riscv_program_puttemp(struct riscv_program *p, enum gdb_regno r);
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