armv7a: Improve parsing of MPIDR register to avoid error message for Cortex R5
References: - ARM DDI0406C ARMv7 Architecture Reference Manual, section B4.1.106 - ARM DDI0460D Cortex-R5 Technical Reference Manual section 4.3.6 - ARM 100048_0002_0 Cortex-A73 Technical Reference Manual section 4.5.2 Tested on: TMS570LC4357 Change-Id: Ie0d45fb697697f78cc4ad4e7a0116be9772590ba Signed-off-by: Tommy Vestermark <tov@vestermark.dk> Reviewed-on: http://openocd.zylin.com/5108 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
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@ -307,23 +307,21 @@ static int armv7a_read_mpidr(struct target *target)
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if (retval != ERROR_OK)
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goto done;
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/* ARMv7R uses a different format for MPIDR.
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* When configured uniprocessor (most R cores) it reads as 0.
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* This will need to be implemented for multiprocessor ARMv7R cores. */
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if (armv7a->is_armv7r) {
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if (mpidr)
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LOG_ERROR("MPIDR nonzero in ARMv7-R target");
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goto done;
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}
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if (mpidr & 1<<31) {
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/* Is register in Multiprocessing Extensions register format? */
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if (mpidr & MPIDR_MP_EXT) {
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LOG_DEBUG("%s: MPIDR 0x%" PRIx32, target_name(target), mpidr);
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armv7a->multi_processor_system = (mpidr >> 30) & 1;
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armv7a->multi_threading_processor = (mpidr >> 24) & 1;
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armv7a->level2_id = (mpidr >> 16) & 0xf;
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armv7a->cluster_id = (mpidr >> 8) & 0xf;
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armv7a->cpu_id = mpidr & 0x3;
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LOG_INFO("%s cluster %x core %x %s", target_name(target),
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armv7a->cpu_id = mpidr & 0xf;
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LOG_INFO("%s: MPIDR level2 %x, cluster %x, core %x, %s, %s",
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target_name(target),
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armv7a->level2_id,
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armv7a->cluster_id,
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armv7a->cpu_id,
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armv7a->multi_processor_system == 0 ? "multi core" : "mono core");
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armv7a->multi_processor_system == 0 ? "multi core" : "mono core",
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armv7a->multi_threading_processor == 1 ? "SMT" : "no SMT");
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} else
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LOG_ERROR("MPIDR not in multiprocessor format");
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@ -108,6 +108,8 @@ struct armv7a_common {
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struct adiv5_ap *debug_ap;
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/* mdir */
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uint8_t multi_processor_system;
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uint8_t multi_threading_processor;
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uint8_t level2_id;
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uint8_t cluster_id;
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uint8_t cpu_id;
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bool is_armv7r;
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@ -183,6 +185,9 @@ static inline bool is_armv7a(struct armv7a_common *armv7a)
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#define DBG_VCR_PREF_ABORT_MASK ((1 << 27) | (1 << 3))
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#define DBG_VCR_SVC_MASK ((1 << 26) | (1 << 2))
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/* Masks for Multiprocessor Affinity Register */
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#define MPIDR_MP_EXT (1UL << 31)
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int armv7a_arch_state(struct target *target);
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int armv7a_identify_cache(struct target *target);
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int armv7a_init_arch_info(struct target *target, struct armv7a_common *armv7a);
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