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riscv-openocd
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Restore value of temporary register (s0) in examine OpenOCD procedure in case of core can not execute 64 bit instruction.

This commit is contained in:
Dmitry Ryzhov 2017-06-30 19:15:58 +03:00
parent 4e2e730abe
commit 7d451e00f5
1 changed files with 8 additions and 0 deletions
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8
src/target/riscv/riscv-013.c
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@ -1175,6 +1175,12 @@ static int examine(struct target *target)
* In order to make this work we first need to */ * In order to make this work we first need to */
int offset = (progbuf_addr % 8 == 0) ? -4 : 0; int offset = (progbuf_addr % 8 == 0) ? -4 : 0;
/* This program uses a temporary register. If the core can not
* execute 64 bit instruction, the original value of temporary
* register will not be restored due to an exception. So we have to
* restore it manually in that case. */
uint64_t s0 = riscv_get_register(target, GDB_REGNO_S0);
struct riscv_program program64; struct riscv_program program64;
riscv_program_init(&program64, target); riscv_program_init(&program64, target);
riscv_program_csrrw(&program64, GDB_REGNO_S0, GDB_REGNO_S0, GDB_REGNO_DSCRATCH); riscv_program_csrrw(&program64, GDB_REGNO_S0, GDB_REGNO_S0, GDB_REGNO_DSCRATCH);
@ -1190,6 +1196,8 @@ static int examine(struct target *target)
+ dmi_read(target, DMI_PROGBUF0 + (4 + offset) / 4) + dmi_read(target, DMI_PROGBUF0 + (4 + offset) / 4)
- 4; - 4;
r->xlen[i] = 64; r->xlen[i] = 64;
} else {
riscv_set_register(target, GDB_REGNO_S0, s0);
} }
/* Display this as early as possible to help people who are using /* Display this as early as possible to help people who are using