From 7d451e00f5c94a8f72f5abfd80a467e0e6a39bc6 Mon Sep 17 00:00:00 2001 From: Dmitry Ryzhov Date: Fri, 30 Jun 2017 19:15:58 +0300 Subject: [PATCH] Restore value of temporary register (s0) in examine OpenOCD procedure in case of core can not execute 64 bit instruction. --- src/target/riscv/riscv-013.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/src/target/riscv/riscv-013.c b/src/target/riscv/riscv-013.c index 60846debe..f45ba4fd5 100644 --- a/src/target/riscv/riscv-013.c +++ b/src/target/riscv/riscv-013.c @@ -1175,6 +1175,12 @@ static int examine(struct target *target) * In order to make this work we first need to */ int offset = (progbuf_addr % 8 == 0) ? -4 : 0; + /* This program uses a temporary register. If the core can not + * execute 64 bit instruction, the original value of temporary + * register will not be restored due to an exception. So we have to + * restore it manually in that case. */ + uint64_t s0 = riscv_get_register(target, GDB_REGNO_S0); + struct riscv_program program64; riscv_program_init(&program64, target); riscv_program_csrrw(&program64, GDB_REGNO_S0, GDB_REGNO_S0, GDB_REGNO_DSCRATCH); @@ -1190,6 +1196,8 @@ static int examine(struct target *target) + dmi_read(target, DMI_PROGBUF0 + (4 + offset) / 4) - 4; r->xlen[i] = 64; + } else { + riscv_set_register(target, GDB_REGNO_S0, s0); } /* Display this as early as possible to help people who are using