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Don't rely on the RTOS hartid for the register cache

This commit is contained in:
Palmer Dabbelt 2018-05-30 07:04:14 -07:00
parent 06bc6cccd4
commit 6d9e69499f
1 changed files with 1 additions and 2 deletions
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3
src/target/riscv/riscv.c
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@ -1755,8 +1755,7 @@ int riscv_set_current_hartid(struct target *target, int hartid)
/* Avoid invalidating the register cache all the time. */ /* Avoid invalidating the register cache all the time. */
if (r->registers_initialized if (r->registers_initialized
&& (!riscv_rtos_enabled(target) || (previous_hartid == hartid)) && (!riscv_rtos_enabled(target) || (previous_hartid == hartid))
&& target->reg_cache->reg_list[GDB_REGNO_ZERO].size == (unsigned)riscv_xlen(target) && target->reg_cache->reg_list[GDB_REGNO_ZERO].size == (unsigned)riscv_xlen(target)) {
&& (!riscv_rtos_enabled(target) || (r->rtos_hartid != -1))) {
return ERROR_OK; return ERROR_OK;
} else } else
LOG_DEBUG("Initializing registers: xlen=%d", riscv_xlen(target)); LOG_DEBUG("Initializing registers: xlen=%d", riscv_xlen(target));