From 6d9e69499f3f6810434c1eb5acf69d6275fddfd0 Mon Sep 17 00:00:00 2001 From: Palmer Dabbelt Date: Wed, 30 May 2018 07:04:14 -0700 Subject: [PATCH] Don't rely on the RTOS hartid for the register cache --- src/target/riscv/riscv.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/target/riscv/riscv.c b/src/target/riscv/riscv.c index 74f1c7eca..1d83badf0 100644 --- a/src/target/riscv/riscv.c +++ b/src/target/riscv/riscv.c @@ -1755,8 +1755,7 @@ int riscv_set_current_hartid(struct target *target, int hartid) /* Avoid invalidating the register cache all the time. */ if (r->registers_initialized && (!riscv_rtos_enabled(target) || (previous_hartid == hartid)) - && target->reg_cache->reg_list[GDB_REGNO_ZERO].size == (unsigned)riscv_xlen(target) - && (!riscv_rtos_enabled(target) || (r->rtos_hartid != -1))) { + && target->reg_cache->reg_list[GDB_REGNO_ZERO].size == (unsigned)riscv_xlen(target)) { return ERROR_OK; } else LOG_DEBUG("Initializing registers: xlen=%d", riscv_xlen(target));