David Brownell <david-b@pacbell.net>:
Add configuration for an old AT91rm9200 board, the Cogent CSB 337. Worth noting from the OpenOCD perspective: - It got a real hardware trace port connector; wired up here as much as we can, lacking inexpensive trace-aware dongles. - This is the first in-tree use of the "arm920t cp15" command. It adjusts the CPU clocking and enables i-cache, which gives more than 4x speedup after booting Linux; it's visible even just running U-Boot. git-svn-id: svn://svn.berlios.de/openocd/trunk@2134 b42882b7-edfa-0310-969c-e2dbd0fdcd60
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# Cogent CSB337
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# http://cogcomp.com/csb_csb337.htm
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source [find target/at91rm9200.cfg]
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# boots from NOR on CS0: 8 MBytes CFI flash, 16-bit bus
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flash bank cfi 0x10000000 0x00800000 2 2 $_TARGETNAME
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# ETM9 trace port connector present on this board, 16 data pins.
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if { [info exists ETM_DRIVER] } {
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etm config $_TARGETNAME 16 normal half $ETM_DRIVER
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# OpenOCD may someday support a real trace port driver...
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# system config file would need to configure it.
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} else {
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etm config $_TARGETNAME 16 normal half dummy
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etm_dummy config $_TARGETNAME
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}
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proc csb337_clk_init { } {
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# CPU is in Slow Clock Mode (32KiHz) ... needs slow JTAG clock
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jtag_khz 8
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# CKGR_MOR: start main oscillator (3.6864 MHz)
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mww 0xfffffc20 0xff01
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sleep 10
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# CKGR_PLLAR: start PLL A for CPU and peripherals (184.32 MHz)
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mww 0xfffffc28 0x20313e01
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# CKGR_PLLBR: start PLL B for USB timing (96 MHz, with div2)
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mww 0xfffffc2c 0x12703e18
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# let PLLs lock
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sleep 10
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# PMC_MCKR: switch to CPU clock = PLLA, master clock = CPU/4
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mww 0xfffffc30 0x0302
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sleep 20
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# CPU is in Normal Mode ... allows faster JTAG clock speed
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jtag_khz 40000
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}
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proc csb337_nor_init { } {
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# SMC_CSR0: adjust timings (10 wait states)
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mww 0xffffff70 0x1100318a
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flash probe 0
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}
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proc csb337_sdram_init { } {
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# enable PIOC clock
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mww 0xfffffc10 0x0010
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# PC31..PC16 are D31..D16, with internal pullups like D15..D0
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mww 0xfffff870 0xffff0000
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mww 0xfffff874 0x0
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mww 0xfffff804 0xffff0000
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# SDRC_CR: set timings
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mww 0xffffff98 0x2188b0d5
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# SDRC_MR: issue all banks precharge to SDRAM
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mww 0xffffff90 2
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mww 0x20000000 0
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# SDRC_MR: 8 autorefresh cycles
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mww 0xffffff90 4
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mww 0x20000000 0
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mww 0x20000000 0
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mww 0x20000000 0
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mww 0x20000000 0
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mww 0x20000000 0
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mww 0x20000000 0
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mww 0x20000000 0
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mww 0x20000000 0
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# SDRC_MR: set SDRAM mode registers (CAS, burst len, etc)
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mww 0xffffff90 3
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mww 0x20000080 0
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# SDRC_TR: set refresh rate
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mww 0xffffff94 0x200
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mww 0x20000000 0
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# SDRC_MR: normal mode, 32 bit bus
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mww 0xffffff90 0
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mww 0x20000000 0
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}
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# The rm9200 chip has just been reset. Bring it up far enough
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# that we can write flash or run code from SDRAM.
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proc csb337_reset_init { } {
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csb337_clk_init
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# EBI_CSA: CS0 = NOR, CS1 = SDRAM
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mww 0xffffff60 0x02
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csb337_nor_init
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csb337_sdram_init
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# Update CP15 control register ... we don't seem to be able to
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# read/modify/write its value through a TCL variable, so just
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# write it. Fields are zero unless listed here ... and note
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# that OpenOCD numbers this register "2", not "1" (!).
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#
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# - Core to use Async Clocking mode (so it uses 184 MHz most
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# of the time instead of limiting to the master clock rate):
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# iA(31) = 1, nF(30) = 1
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# - Icache on (it's disabled now, slowing i-fetches)
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# I(12) = 1
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# - Reserved/ones
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# 6:3 = 1
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# - Alignment traps enabled
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# A(1) = 1
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arm920t cp15 2 0xc000107a
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}
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$_TARGETNAME configure -event reset-init {csb337_reset_init}
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# vim:syntax tcl
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@ -1,4 +1,6 @@
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# script for str9
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# For more information about the configuration files, take a look at:
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# openocd.texi
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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@ -19,52 +21,74 @@ jtag_nsrst_delay 100
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jtag_ntrst_delay 100
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#use combined on interfaces or targets that can't set TRST/SRST separately
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reset_config trst_and_srst
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#reset_config trst_and_srst
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if { [info exists FLASHTAPID ] } {
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set _FLASHTAPID $FLASHTAPID
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} else {
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set _FLASHTAPID 0x04570041
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}
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jtag newtap $_CHIPNAME flash -irlen 8 -ircapture 0x1 -irmask 0x1 -expected-id $_FLASHTAPID
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jtag newtap $_CHIPNAME flash \
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-irlen 8 -ircapture 0x1 -irmask 0x1 \
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-expected-id $_FLASHTAPID
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if { [info exists CPUTAPID ] } {
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set _CPUTAPID $CPUTAPID
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} else {
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set _CPUTAPID 0x25966041
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}
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jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
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jtag newtap $_CHIPNAME cpu \
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-irlen 4 -ircapture 0x1 -irmask 0xf \
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-expected-id $_CPUTAPID
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if { [info exists BSTAPID ] } {
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set _BSTAPID $BSTAPID
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set _BSTAPID1 $BSTAPID
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set _BSTAPID2 $BSTAPID
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} else {
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set _BSTAPID 0x1457f041
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set _BSTAPID1 0x1457f041
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set _BSTAPID2 0x2457f041
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}
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jtag newtap $_CHIPNAME bs -irlen 5 -ircapture 0x1 -irmask 0x1 -expected-id $_BSTAPID
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jtag newtap $_CHIPNAME bs \
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-irlen 5 -ircapture 0x1 -irmask 0x1 \
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-expected-id $_BSTAPID1 -expected-id $_BSTAPID2
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set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
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target create $_TARGETNAME arm966e -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm966e
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target create $_TARGETNAME arm966e \
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-endian $_ENDIAN \
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-chain-position $_TARGETNAME \
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-variant arm966e
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$_TARGETNAME configure -event reset-start { jtag_rclk 16 }
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$_TARGETNAME configure -event reset-init {
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# We can increase speed now that we know the target is halted.
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#jtag_rclk 3000
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# -- Enable 96K RAM
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# PFQBC enabled / DTCM & AHB wait-states disabled
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mww 0x5C002034 0x0191
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proc str9x_config { } {
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# -- Enable 96K RAM w/:
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# PFQBC enabled / DTCM & AHB wait-states disabled
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mww 0x5C002034 0x0191
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# PFQBC disabled / DTCM & AHB wait-states enabled
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#mww 0x5C002034 0x0196
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str9x flash_config 0 4 2 0 0x80000
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flash protect 0 0 7 off
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# 256K/32k
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str9x flash_config 0 3 2 0 0x40000
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# 512K/32K
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#str9x flash_config 0 4 2 0 0x80000
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}
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$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x50000000 -work-area-size 16384 -work-area-backup 0
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proc str9x_init { } {
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# enable RTCK
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jtag_rclk 0
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str9x_config
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}
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$_TARGETNAME configure -event reset-init str9x_init
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$_TARGETNAME configure \
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-work-area-virt 0 \
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-work-area-phys 0x50000000 \
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-work-area-size 16384 \
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-work-area-backup 0
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#flash bank str9x <base> <size> 0 0 <target#> <variant>
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flash bank str9x 0x00000000 0x00080000 0 0 0
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flash bank str9x 0x00080000 0x00008000 0 0 0
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flash bank str9x 0x00000000 0x00040000 0 0 0
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flash bank str9x 0x00040000 0x00008000 0 0 0
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# For more information about the configuration files, take a look at:
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# openocd.texi
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