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arm_adi_v5: Remove all mem_ap_sel_* functions 

All mem_ap_* functions now make sure the SELECT register is updated with
the AP number that it's operating on. This shouldn't have to be handled
explicitly.

Change-Id: Ib193d8930fabb6a25715064355f98258c9580b5d
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/3153
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
This commit is contained in:
Andreas Fritiofson 2015-12-28 18:43:22 +01:00
parent 4da8915fb9
commit 4a7bb931e3
6 changed files with 178 additions and 206 deletions
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6
src/flash/nor/at91sam4l.c
View File

@ -659,14 +659,14 @@ COMMAND_HANDLER(sam4l_handle_reset_deassert)
* After vectreset SMAP release is not needed however makes no harm
*/
if (target->reset_halt && (jtag_reset_config & RESET_HAS_SRST)) {
retval = mem_ap_sel_write_u32(armv7m->debug_ap, DCB_DHCSR, DBGKEY | C_HALT | C_DEBUGEN);
retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DHCSR, DBGKEY | C_HALT | C_DEBUGEN);
if (retval == ERROR_OK)
retval = mem_ap_sel_write_atomic_u32(armv7m->debug_ap, DCB_DEMCR,
retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DEMCR,
TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
/* do not return on error here, releasing SMAP reset is more important */
}
int retval2 = mem_ap_sel_write_atomic_u32(armv7m->debug_ap, SMAP_SCR, SMAP_SCR_HCR);
int retval2 = mem_ap_write_atomic_u32(armv7m->debug_ap, SMAP_SCR, SMAP_SCR_HCR);
if (retval2 != ERROR_OK)
return retval2;

4
src/flash/nor/at91samd.c
View File

@ -999,9 +999,9 @@ COMMAND_HANDLER(samd_handle_reset_deassert)
* After vectreset DSU release is not needed however makes no harm
*/
if (target->reset_halt && (jtag_reset_config & RESET_HAS_SRST)) {
retval = mem_ap_sel_write_u32(armv7m->debug_ap, DCB_DHCSR, DBGKEY | C_HALT | C_DEBUGEN);
retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DHCSR, DBGKEY | C_HALT | C_DEBUGEN);
if (retval == ERROR_OK)
retval = mem_ap_sel_write_u32(armv7m->debug_ap, DCB_DEMCR,
retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DEMCR,
TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
/* do not return on error here, releasing DSU reset is more important */
}

109
src/target/arm_adi_v5.c
View File

@ -176,7 +176,7 @@ static int mem_ap_setup_transfer(struct adiv5_ap *ap, uint32_t csw, uint32_t tar
/**
* Asynchronous (queued) read of a word from memory or a system register.
*
* @param dap The DAP connected to the MEM-AP performing the read.
* @param ap The MEM-AP to access.
* @param address Address of the 32-bit word to read; it must be
* readable by the currently selected MEM-AP.
* @param value points to where the word will be stored when the
@ -184,11 +184,13 @@ static int mem_ap_setup_transfer(struct adiv5_ap *ap, uint32_t csw, uint32_t tar
*
* @return ERROR_OK for success. Otherwise a fault code.
*/
static int mem_ap_read_u32(struct adiv5_ap *ap, uint32_t address,
int mem_ap_read_u32(struct adiv5_ap *ap, uint32_t address,
uint32_t *value)
{
int retval;
dap_ap_select(ap->dap, ap->ap_num);
/* Use banked addressing (REG_BDx) to avoid some link traffic
* (updating TAR) when reading several consecutive addresses.
*/
@ -204,7 +206,7 @@ static int mem_ap_read_u32(struct adiv5_ap *ap, uint32_t address,
* Synchronous read of a word from memory or a system register.
* As a side effect, this flushes any queued transactions.
*
* @param dap The DAP connected to the MEM-AP performing the read.
* @param ap The MEM-AP to access.
* @param address Address of the 32-bit word to read; it must be
* readable by the currently selected MEM-AP.
* @param value points to where the result will be stored.
@ -212,7 +214,7 @@ static int mem_ap_read_u32(struct adiv5_ap *ap, uint32_t address,
* @return ERROR_OK for success; *value holds the result.
* Otherwise a fault code.
*/
static int mem_ap_read_atomic_u32(struct adiv5_ap *ap, uint32_t address,
int mem_ap_read_atomic_u32(struct adiv5_ap *ap, uint32_t address,
uint32_t *value)
{
int retval;
@ -227,7 +229,7 @@ static int mem_ap_read_atomic_u32(struct adiv5_ap *ap, uint32_t address,
/**
* Asynchronous (queued) write of a word to memory or a system register.
*
* @param dap The DAP connected to the MEM-AP.
* @param ap The MEM-AP to access.
* @param address Address to be written; it must be writable by
* the currently selected MEM-AP.
* @param value Word that will be written to the address when transaction
@ -235,11 +237,13 @@ static int mem_ap_read_atomic_u32(struct adiv5_ap *ap, uint32_t address,
*
* @return ERROR_OK for success. Otherwise a fault code.
*/
static int mem_ap_write_u32(struct adiv5_ap *ap, uint32_t address,
int mem_ap_write_u32(struct adiv5_ap *ap, uint32_t address,
uint32_t value)
{
int retval;
dap_ap_select(ap->dap, ap->ap_num);
/* Use banked addressing (REG_BDx) to avoid some link traffic
* (updating TAR) when writing several consecutive addresses.
*/
@ -256,14 +260,14 @@ static int mem_ap_write_u32(struct adiv5_ap *ap, uint32_t address,
* Synchronous write of a word to memory or a system register.
* As a side effect, this flushes any queued transactions.
*
* @param dap The DAP connected to the MEM-AP.
* @param ap The MEM-AP to access.
* @param address Address to be written; it must be writable by
* the currently selected MEM-AP.
* @param value Word that will be written.
*
* @return ERROR_OK for success; the data was written. Otherwise a fault code.
*/
static int mem_ap_write_atomic_u32(struct adiv5_ap *ap, uint32_t address,
int mem_ap_write_atomic_u32(struct adiv5_ap *ap, uint32_t address,
uint32_t value)
{
int retval = mem_ap_write_u32(ap, address, value);
@ -277,7 +281,7 @@ static int mem_ap_write_atomic_u32(struct adiv5_ap *ap, uint32_t address,
/**
* Synchronous write of a block of memory, using a specific access size.
*
* @param dap The DAP connected to the MEM-AP.
* @param ap The MEM-AP to access.
* @param buffer The data buffer to write. No particular alignment is assumed.
* @param size Which access size to use, in bytes. 1, 2 or 4.
* @param count The number of writes to do (in size units, not bytes).
@ -325,6 +329,8 @@ static int mem_ap_write(struct adiv5_ap *ap, const uint8_t *buffer, uint32_t siz
if (ap->unaligned_access_bad && (address % size != 0))
return ERROR_TARGET_UNALIGNED_ACCESS;
dap_ap_select(ap->dap, ap->ap_num);
retval = mem_ap_setup_tar(ap, address ^ addr_xor);
if (retval != ERROR_OK)
return retval;
@ -408,7 +414,7 @@ static int mem_ap_write(struct adiv5_ap *ap, const uint8_t *buffer, uint32_t siz
/**
* Synchronous read of a block of memory, using a specific access size.
*
* @param dap The DAP connected to the MEM-AP.
* @param ap The MEM-AP to access.
* @param buffer The data buffer to receive the data. No particular alignment is assumed.
* @param size Which access size to use, in bytes. 1, 2 or 4.
* @param count The number of reads to do (in size units, not bytes).
@ -456,6 +462,8 @@ static int mem_ap_read(struct adiv5_ap *ap, uint8_t *buffer, uint32_t size, uint
return ERROR_FAIL;
}
dap_ap_select(ap->dap, ap->ap_num);
retval = mem_ap_setup_tar(ap, address);
if (retval != ERROR_OK) {
free(read_buf);
@ -556,62 +564,27 @@ static int mem_ap_read(struct adiv5_ap *ap, uint8_t *buffer, uint32_t size, uint
return retval;
}
/*--------------------------------------------------------------------*/
/* Wrapping function with selection of AP */
/*--------------------------------------------------------------------*/
int mem_ap_sel_read_u32(struct adiv5_ap *ap,
uint32_t address, uint32_t *value)
{
dap_ap_select(ap->dap, ap->ap_num);
return mem_ap_read_u32(ap, address, value);
}
int mem_ap_sel_write_u32(struct adiv5_ap *ap,
uint32_t address, uint32_t value)
{
dap_ap_select(ap->dap, ap->ap_num);
return mem_ap_write_u32(ap, address, value);
}
int mem_ap_sel_read_atomic_u32(struct adiv5_ap *ap,
uint32_t address, uint32_t *value)
{
dap_ap_select(ap->dap, ap->ap_num);
return mem_ap_read_atomic_u32(ap, address, value);
}
int mem_ap_sel_write_atomic_u32(struct adiv5_ap *ap,
uint32_t address, uint32_t value)
{
dap_ap_select(ap->dap, ap->ap_num);
return mem_ap_write_atomic_u32(ap, address, value);
}
int mem_ap_sel_read_buf(struct adiv5_ap *ap,
int mem_ap_read_buf(struct adiv5_ap *ap,
uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
{
dap_ap_select(ap->dap, ap->ap_num);
return mem_ap_read(ap, buffer, size, count, address, true);
}
int mem_ap_sel_write_buf(struct adiv5_ap *ap,
int mem_ap_write_buf(struct adiv5_ap *ap,
const uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
{
dap_ap_select(ap->dap, ap->ap_num);
return mem_ap_write(ap, buffer, size, count, address, true);
}
int mem_ap_sel_read_buf_noincr(struct adiv5_ap *ap,
int mem_ap_read_buf_noincr(struct adiv5_ap *ap,
uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
{
dap_ap_select(ap->dap, ap->ap_num);
return mem_ap_read(ap, buffer, size, count, address, false);
}
int mem_ap_sel_write_buf_noincr(struct adiv5_ap *ap,
int mem_ap_write_buf_noincr(struct adiv5_ap *ap,
const uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
{
dap_ap_select(ap->dap, ap->ap_num);
return mem_ap_write(ap, buffer, size, count, address, false);
}
@ -902,7 +875,7 @@ int dap_lookup_cs_component(struct adiv5_ap *ap,
ap_old = dap_ap_get_select(dap);
do {
retval = mem_ap_sel_read_atomic_u32(ap, (dbgbase&0xFFFFF000) |
retval = mem_ap_read_atomic_u32(ap, (dbgbase&0xFFFFF000) |
entry_offset, &romentry);
if (retval != ERROR_OK)
return retval;
@ -912,7 +885,7 @@ int dap_lookup_cs_component(struct adiv5_ap *ap,
if (romentry & 0x1) {
uint32_t c_cid1;
retval = mem_ap_sel_read_atomic_u32(ap, component_base | 0xff4, &c_cid1);
retval = mem_ap_read_atomic_u32(ap, component_base | 0xff4, &c_cid1);
if (retval != ERROR_OK) {
LOG_ERROR("Can't read component with base address 0x%" PRIx32
", the corresponding core might be turned off", component_base);
@ -927,7 +900,7 @@ int dap_lookup_cs_component(struct adiv5_ap *ap,
return retval;
}
retval = mem_ap_sel_read_atomic_u32(ap,
retval = mem_ap_read_atomic_u32(ap,
(component_base & 0xfffff000) | 0xfcc,
&devtype);
if (retval != ERROR_OK)
@ -975,19 +948,19 @@ static int dap_rom_display(struct command_context *cmd_ctx,
command_print(cmd_ctx, "\t%sROM table in legacy format", tabs);
/* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
retval = mem_ap_sel_read_u32(ap, (dbgbase&0xFFFFF000) | 0xFF0, &cid0);
retval = mem_ap_read_u32(ap, (dbgbase&0xFFFFF000) | 0xFF0, &cid0);
if (retval != ERROR_OK)
return retval;
retval = mem_ap_sel_read_u32(ap, (dbgbase&0xFFFFF000) | 0xFF4, &cid1);
retval = mem_ap_read_u32(ap, (dbgbase&0xFFFFF000) | 0xFF4, &cid1);
if (retval != ERROR_OK)
return retval;
retval = mem_ap_sel_read_u32(ap, (dbgbase&0xFFFFF000) | 0xFF8, &cid2);
retval = mem_ap_read_u32(ap, (dbgbase&0xFFFFF000) | 0xFF8, &cid2);
if (retval != ERROR_OK)
return retval;
retval = mem_ap_sel_read_u32(ap, (dbgbase&0xFFFFF000) | 0xFFC, &cid3);
retval = mem_ap_read_u32(ap, (dbgbase&0xFFFFF000) | 0xFFC, &cid3);
if (retval != ERROR_OK)
return retval;
retval = mem_ap_sel_read_u32(ap, (dbgbase&0xFFFFF000) | 0xFCC, &memtype);
retval = mem_ap_read_u32(ap, (dbgbase&0xFFFFF000) | 0xFCC, &memtype);
if (retval != ERROR_OK)
return retval;
retval = dap_run(dap);
@ -1009,7 +982,7 @@ static int dap_rom_display(struct command_context *cmd_ctx,
/* Now we read ROM table entries from dbgbase&0xFFFFF000) | 0x000 until we get 0x00000000 */
for (entry_offset = 0; ; entry_offset += 4) {
retval = mem_ap_sel_read_atomic_u32(ap, (dbgbase&0xFFFFF000) | entry_offset, &romentry);
retval = mem_ap_read_atomic_u32(ap, (dbgbase&0xFFFFF000) | entry_offset, &romentry);
if (retval != ERROR_OK)
return retval;
command_print(cmd_ctx, "\t%sROMTABLE[0x%x] = 0x%" PRIx32 "",
@ -1024,43 +997,43 @@ static int dap_rom_display(struct command_context *cmd_ctx,
component_base = (dbgbase & 0xFFFFF000) + (romentry & 0xFFFFF000);
/* IDs are in last 4K section */
retval = mem_ap_sel_read_atomic_u32(ap, component_base + 0xFE0, &c_pid0);
retval = mem_ap_read_atomic_u32(ap, component_base + 0xFE0, &c_pid0);
if (retval != ERROR_OK) {
command_print(cmd_ctx, "\t%s\tCan't read component with base address 0x%" PRIx32
", the corresponding core might be turned off", tabs, component_base);
continue;
}
c_pid0 &= 0xff;
retval = mem_ap_sel_read_atomic_u32(ap, component_base + 0xFE4, &c_pid1);
retval = mem_ap_read_atomic_u32(ap, component_base + 0xFE4, &c_pid1);
if (retval != ERROR_OK)
return retval;
c_pid1 &= 0xff;
retval = mem_ap_sel_read_atomic_u32(ap, component_base + 0xFE8, &c_pid2);
retval = mem_ap_read_atomic_u32(ap, component_base + 0xFE8, &c_pid2);
if (retval != ERROR_OK)
return retval;
c_pid2 &= 0xff;
retval = mem_ap_sel_read_atomic_u32(ap, component_base + 0xFEC, &c_pid3);
retval = mem_ap_read_atomic_u32(ap, component_base + 0xFEC, &c_pid3);
if (retval != ERROR_OK)
return retval;
c_pid3 &= 0xff;
retval = mem_ap_sel_read_atomic_u32(ap, component_base + 0xFD0, &c_pid4);
retval = mem_ap_read_atomic_u32(ap, component_base + 0xFD0, &c_pid4);
if (retval != ERROR_OK)
return retval;
c_pid4 &= 0xff;
retval = mem_ap_sel_read_atomic_u32(ap, component_base + 0xFF0, &c_cid0);
retval = mem_ap_read_atomic_u32(ap, component_base + 0xFF0, &c_cid0);
if (retval != ERROR_OK)
return retval;
c_cid0 &= 0xff;
retval = mem_ap_sel_read_atomic_u32(ap, component_base + 0xFF4, &c_cid1);
retval = mem_ap_read_atomic_u32(ap, component_base + 0xFF4, &c_cid1);
if (retval != ERROR_OK)
return retval;
c_cid1 &= 0xff;
retval = mem_ap_sel_read_atomic_u32(ap, component_base + 0xFF8, &c_cid2);
retval = mem_ap_read_atomic_u32(ap, component_base + 0xFF8, &c_cid2);
if (retval != ERROR_OK)
return retval;
c_cid2 &= 0xff;
retval = mem_ap_sel_read_atomic_u32(ap, component_base + 0xFFC, &c_cid3);
retval = mem_ap_read_atomic_u32(ap, component_base + 0xFFC, &c_cid3);
if (retval != ERROR_OK)
return retval;
c_cid3 &= 0xff;
@ -1080,7 +1053,7 @@ static int dap_rom_display(struct command_context *cmd_ctx,
unsigned minor;
const char *major = "Reserved", *subtype = "Reserved";
retval = mem_ap_sel_read_atomic_u32(ap,
retval = mem_ap_read_atomic_u32(ap,
(component_base & 0xfffff000) | 0xfcc,
&devtype);
if (retval != ERROR_OK)

25
src/target/arm_adi_v5.h
View File

@ -455,29 +455,28 @@ static inline uint8_t dap_ap_get_select(struct adiv5_dap *swjdp)
/* AP selection applies to future AP transactions */
void dap_ap_select(struct adiv5_dap *dap, uint8_t ap);
/* Queued MEM-AP memory mapped single word transfers with selection of ap */
int mem_ap_sel_read_u32(struct adiv5_ap *ap,
/* Queued MEM-AP memory mapped single word transfers. */
int mem_ap_read_u32(struct adiv5_ap *ap,
uint32_t address, uint32_t *value);
int mem_ap_sel_write_u32(struct adiv5_ap *ap,
int mem_ap_write_u32(struct adiv5_ap *ap,
uint32_t address, uint32_t value);
/* Synchronous MEM-AP memory mapped single word transfers with selection of ap */
int mem_ap_sel_read_atomic_u32(struct adiv5_ap *ap,
/* Synchronous MEM-AP memory mapped single word transfers. */
int mem_ap_read_atomic_u32(struct adiv5_ap *ap,
uint32_t address, uint32_t *value);
int mem_ap_sel_write_atomic_u32(struct adiv5_ap *ap,
int mem_ap_write_atomic_u32(struct adiv5_ap *ap,
uint32_t address, uint32_t value);
/* Synchronous MEM-AP memory mapped bus block transfers with selection of ap */
int mem_ap_sel_read_buf(struct adiv5_ap *ap,
/* Synchronous MEM-AP memory mapped bus block transfers. */
int mem_ap_read_buf(struct adiv5_ap *ap,
uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address);
int mem_ap_sel_write_buf(struct adiv5_ap *ap,
int mem_ap_write_buf(struct adiv5_ap *ap,
const uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address);
/* Synchronous, non-incrementing buffer functions for accessing fifos, with
* selection of ap */
int mem_ap_sel_read_buf_noincr(struct adiv5_ap *ap,
/* Synchronous, non-incrementing buffer functions for accessing fifos. */
int mem_ap_read_buf_noincr(struct adiv5_ap *ap,
uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address);
int mem_ap_sel_write_buf_noincr(struct adiv5_ap *ap,
int mem_ap_write_buf_noincr(struct adiv5_ap *ap,
const uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address);
/* Create DAP struct */

136
src/target/cortex_a.c
View File

@ -194,11 +194,11 @@ static int cortex_a8_init_debug_access(struct target *target)
/* Unlocking the debug registers for modification
* The debugport might be uninitialised so try twice */
retval = mem_ap_sel_write_atomic_u32(armv7a->debug_ap,
retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_LOCKACCESS, 0xC5ACCE55);
if (retval != ERROR_OK) {
/* try again */
retval = mem_ap_sel_write_atomic_u32(armv7a->debug_ap,
retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_LOCKACCESS, 0xC5ACCE55);
if (retval == ERROR_OK)
LOG_USER(
@ -226,7 +226,7 @@ static int cortex_a_init_debug_access(struct target *target)
switch (cortex_part_num) {
case CORTEX_A7_PARTNUM:
case CORTEX_A15_PARTNUM:
retval = mem_ap_sel_read_atomic_u32(armv7a->debug_ap,
retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_OSLSR,
&dbg_osreg);
if (retval != ERROR_OK)
@ -236,7 +236,7 @@ static int cortex_a_init_debug_access(struct target *target)
if (dbg_osreg & CPUDBG_OSLAR_LK_MASK)
/* Unlocking the DEBUG OS registers for modification */
retval = mem_ap_sel_write_atomic_u32(armv7a->debug_ap,
retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_OSLAR,
0);
break;
@ -252,7 +252,7 @@ static int cortex_a_init_debug_access(struct target *target)
return retval;
/* Clear Sticky Power Down status Bit in PRSR to enable access to
the registers in the Core Power Domain */
retval = mem_ap_sel_read_atomic_u32(armv7a->debug_ap,
retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_PRSR, &dbg_osreg);
LOG_DEBUG("target->coreid %" PRId32 " DBGPRSR 0x%" PRIx32, target->coreid, dbg_osreg);
@ -260,13 +260,13 @@ static int cortex_a_init_debug_access(struct target *target)
return retval;
/* Disable cacheline fills and force cache write-through in debug state */
retval = mem_ap_sel_write_atomic_u32(armv7a->debug_ap,
retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DSCCR, 0);
if (retval != ERROR_OK)
return retval;
/* Disable TLB lookup and refill/eviction in debug state */
retval = mem_ap_sel_write_atomic_u32(armv7a->debug_ap,
retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DSMCR, 0);
if (retval != ERROR_OK)
return retval;
@ -288,7 +288,7 @@ static int cortex_a_wait_instrcmpl(struct target *target, uint32_t *dscr, bool f
long long then = timeval_ms();
while ((*dscr & DSCR_INSTR_COMP) == 0 || force) {
force = false;
int retval = mem_ap_sel_read_atomic_u32(armv7a->debug_ap,
int retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DSCR, dscr);
if (retval != ERROR_OK) {
LOG_ERROR("Could not read DSCR register");
@ -323,14 +323,14 @@ static int cortex_a_exec_opcode(struct target *target,
if (retval != ERROR_OK)
return retval;
retval = mem_ap_sel_write_u32(armv7a->debug_ap,
retval = mem_ap_write_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_ITR, opcode);
if (retval != ERROR_OK)
return retval;
long long then = timeval_ms();
do {
retval = mem_ap_sel_read_atomic_u32(armv7a->debug_ap,
retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DSCR, &dscr);
if (retval != ERROR_OK) {
LOG_ERROR("Could not read DSCR register");
@ -368,7 +368,7 @@ static int cortex_a_read_regs_through_mem(struct target *target, uint32_t addres
if (retval != ERROR_OK)
return retval;
retval = mem_ap_sel_read_buf(armv7a->memory_ap,
retval = mem_ap_read_buf(armv7a->memory_ap,
(uint8_t *)(&regfile[1]), 4, 15, address);
return retval;
@ -419,7 +419,7 @@ static int cortex_a_dap_read_coreregister_u32(struct target *target,
/* Wait for DTRRXfull then read DTRRTX */
long long then = timeval_ms();
while ((dscr & DSCR_DTR_TX_FULL) == 0) {
retval = mem_ap_sel_read_atomic_u32(armv7a->debug_ap,
retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DSCR, &dscr);
if (retval != ERROR_OK)
return retval;
@ -429,7 +429,7 @@ static int cortex_a_dap_read_coreregister_u32(struct target *target,
}
}
retval = mem_ap_sel_read_atomic_u32(armv7a->debug_ap,
retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DTRTX, value);
LOG_DEBUG("read DCC 0x%08" PRIx32, *value);
@ -447,7 +447,7 @@ static int cortex_a_dap_write_coreregister_u32(struct target *target,
LOG_DEBUG("register %i, value 0x%08" PRIx32, regnum, value);
/* Check that DCCRX is not full */
retval = mem_ap_sel_read_atomic_u32(armv7a->debug_ap,
retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DSCR, &dscr);
if (retval != ERROR_OK)
return retval;
@ -465,7 +465,7 @@ static int cortex_a_dap_write_coreregister_u32(struct target *target,
/* Write DTRRX ... sets DSCR.DTRRXfull but exec_opcode() won't care */
LOG_DEBUG("write DCC 0x%08" PRIx32, value);
retval = mem_ap_sel_write_u32(armv7a->debug_ap,
retval = mem_ap_write_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DTRRX, value);
if (retval != ERROR_OK)
return retval;
@ -522,7 +522,7 @@ static int cortex_a_dap_write_memap_register_u32(struct target *target,
int retval;
struct armv7a_common *armv7a = target_to_armv7a(target);
retval = mem_ap_sel_write_atomic_u32(armv7a->debug_ap, address, value);
retval = mem_ap_write_atomic_u32(armv7a->debug_ap, address, value);
return retval;
}
@ -546,7 +546,7 @@ static inline struct cortex_a_common *dpm_to_a(struct arm_dpm *dpm)
static int cortex_a_write_dcc(struct cortex_a_common *a, uint32_t data)
{
LOG_DEBUG("write DCC 0x%08" PRIx32, data);
return mem_ap_sel_write_u32(a->armv7a_common.debug_ap,
return mem_ap_write_u32(a->armv7a_common.debug_ap,
a->armv7a_common.debug_base + CPUDBG_DTRRX, data);
}
@ -562,7 +562,7 @@ static int cortex_a_read_dcc(struct cortex_a_common *a, uint32_t *data,
/* Wait for DTRRXfull */
long long then = timeval_ms();
while ((dscr & DSCR_DTR_TX_FULL) == 0) {
retval = mem_ap_sel_read_atomic_u32(a->armv7a_common.debug_ap,
retval = mem_ap_read_atomic_u32(a->armv7a_common.debug_ap,
a->armv7a_common.debug_base + CPUDBG_DSCR,
&dscr);
if (retval != ERROR_OK)
@ -573,7 +573,7 @@ static int cortex_a_read_dcc(struct cortex_a_common *a, uint32_t *data,
}
}
retval = mem_ap_sel_read_atomic_u32(a->armv7a_common.debug_ap,
retval = mem_ap_read_atomic_u32(a->armv7a_common.debug_ap,
a->armv7a_common.debug_base + CPUDBG_DTRTX, data);
if (retval != ERROR_OK)
return retval;
@ -594,7 +594,7 @@ static int cortex_a_dpm_prepare(struct arm_dpm *dpm)
/* set up invariant: INSTR_COMP is set after ever DPM operation */
long long then = timeval_ms();
for (;; ) {
retval = mem_ap_sel_read_atomic_u32(a->armv7a_common.debug_ap,
retval = mem_ap_read_atomic_u32(a->armv7a_common.debug_ap,
a->armv7a_common.debug_base + CPUDBG_DSCR,
&dscr);
if (retval != ERROR_OK)
@ -881,7 +881,7 @@ static int cortex_a_poll(struct target *target)
target_call_event_callbacks(target, TARGET_EVENT_HALTED);
return retval;
}
retval = mem_ap_sel_read_atomic_u32(armv7a->debug_ap,
retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DSCR, &dscr);
if (retval != ERROR_OK)
return retval;
@ -942,7 +942,7 @@ static int cortex_a_halt(struct target *target)
* Tell the core to be halted by writing DRCR with 0x1
* and then wait for the core to be halted.
*/
retval = mem_ap_sel_write_atomic_u32(armv7a->debug_ap,
retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DRCR, DRCR_HALT);
if (retval != ERROR_OK)
return retval;
@ -950,19 +950,19 @@ static int cortex_a_halt(struct target *target)
/*
* enter halting debug mode
*/
retval = mem_ap_sel_read_atomic_u32(armv7a->debug_ap,
retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DSCR, &dscr);
if (retval != ERROR_OK)
return retval;
retval = mem_ap_sel_write_atomic_u32(armv7a->debug_ap,
retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DSCR, dscr | DSCR_HALT_DBG_MODE);
if (retval != ERROR_OK)
return retval;
long long then = timeval_ms();
for (;; ) {
retval = mem_ap_sel_read_atomic_u32(armv7a->debug_ap,
retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DSCR, &dscr);
if (retval != ERROR_OK)
return retval;
@ -1087,7 +1087,7 @@ static int cortex_a_internal_restart(struct target *target)
* disable IRQs by default, with optional override...
*/
retval = mem_ap_sel_read_atomic_u32(armv7a->debug_ap,
retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DSCR, &dscr);
if (retval != ERROR_OK)
return retval;
@ -1095,12 +1095,12 @@ static int cortex_a_internal_restart(struct target *target)
if ((dscr & DSCR_INSTR_COMP) == 0)
LOG_ERROR("DSCR InstrCompl must be set before leaving debug!");
retval = mem_ap_sel_write_atomic_u32(armv7a->debug_ap,
retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DSCR, dscr & ~DSCR_ITR_EN);
if (retval != ERROR_OK)
return retval;
retval = mem_ap_sel_write_atomic_u32(armv7a->debug_ap,
retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DRCR, DRCR_RESTART |
DRCR_CLEAR_EXCEPTIONS);
if (retval != ERROR_OK)
@ -1108,7 +1108,7 @@ static int cortex_a_internal_restart(struct target *target)
long long then = timeval_ms();
for (;; ) {
retval = mem_ap_sel_read_atomic_u32(armv7a->debug_ap,
retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DSCR, &dscr);
if (retval != ERROR_OK)
return retval;
@ -1199,7 +1199,7 @@ static int cortex_a_debug_entry(struct target *target)
LOG_DEBUG("dscr = 0x%08" PRIx32, cortex_a->cpudbg_dscr);
/* REVISIT surely we should not re-read DSCR !! */
retval = mem_ap_sel_read_atomic_u32(armv7a->debug_ap,
retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DSCR, &dscr);
if (retval != ERROR_OK)
return retval;
@ -1211,7 +1211,7 @@ static int cortex_a_debug_entry(struct target *target)
/* Enable the ITR execution once we are in debug mode */
dscr |= DSCR_ITR_EN;
retval = mem_ap_sel_write_atomic_u32(armv7a->debug_ap,
retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DSCR, dscr);
if (retval != ERROR_OK)
return retval;
@ -1223,7 +1223,7 @@ static int cortex_a_debug_entry(struct target *target)
if (target->debug_reason == DBG_REASON_WATCHPOINT) {
uint32_t wfar;
retval = mem_ap_sel_read_atomic_u32(armv7a->debug_ap,
retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_WFAR,
&wfar);
if (retval != ERROR_OK)
@ -1345,7 +1345,7 @@ int cortex_a_set_dscr_bits(struct target *target, unsigned long bit_mask, unsign
uint32_t dscr;
/* Read DSCR */
int retval = mem_ap_sel_read_atomic_u32(armv7a->debug_ap,
int retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DSCR, &dscr);
if (ERROR_OK != retval)
return retval;
@ -1356,7 +1356,7 @@ int cortex_a_set_dscr_bits(struct target *target, unsigned long bit_mask, unsign
dscr |= value & bit_mask;
/* write new DSCR */
retval = mem_ap_sel_write_atomic_u32(armv7a->debug_ap,
retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DSCR, dscr);
return retval;
}
@ -1937,7 +1937,7 @@ static int cortex_a_set_dcc_mode(struct target *target, uint32_t mode, uint32_t
uint32_t new_dscr = (*dscr & ~DSCR_EXT_DCC_MASK) | mode;
if (new_dscr != *dscr) {
struct armv7a_common *armv7a = target_to_armv7a(target);
int retval = mem_ap_sel_write_atomic_u32(armv7a->debug_ap,
int retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DSCR, new_dscr);
if (retval == ERROR_OK)
*dscr = new_dscr;
@ -1956,7 +1956,7 @@ static int cortex_a_wait_dscr_bits(struct target *target, uint32_t mask,
int retval;
while ((*dscr & mask) != value) {
retval = mem_ap_sel_read_atomic_u32(armv7a->debug_ap,
retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DSCR, dscr);
if (retval != ERROR_OK)
return retval;
@ -1994,7 +1994,7 @@ static int cortex_a_read_copro(struct target *target, uint32_t opcode,
return retval;
/* Read the value transferred to DTRTX. */
retval = mem_ap_sel_read_atomic_u32(armv7a->debug_ap,
retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DTRTX, data);
if (retval != ERROR_OK)
return retval;
@ -2029,7 +2029,7 @@ static int cortex_a_write_copro(struct target *target, uint32_t opcode,
struct armv7a_common *armv7a = target_to_armv7a(target);
/* Write the value into DTRRX. */
retval = mem_ap_sel_write_atomic_u32(armv7a->debug_ap,
retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DTRRX, data);
if (retval != ERROR_OK)
return retval;
@ -2132,7 +2132,7 @@ static int cortex_a_write_apb_ab_memory_slow(struct target *target,
data = target_buffer_get_u16(target, buffer);
else
data = target_buffer_get_u32(target, buffer);
retval = mem_ap_sel_write_atomic_u32(armv7a->debug_ap,
retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DTRRX, data);
if (retval != ERROR_OK)
return retval;
@ -2192,13 +2192,13 @@ static int cortex_a_write_apb_ab_memory_fast(struct target *target,
return retval;
/* Latch STC instruction. */
retval = mem_ap_sel_write_atomic_u32(armv7a->debug_ap,
retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_ITR, ARMV4_5_STC(0, 1, 0, 1, 14, 5, 0, 4));
if (retval != ERROR_OK)
return retval;
/* Transfer all the data and issue all the instructions. */
return mem_ap_sel_write_buf_noincr(armv7a->debug_ap, buffer,
return mem_ap_write_buf_noincr(armv7a->debug_ap, buffer,
4, count, armv7a->debug_base + CPUDBG_DTRRX);
}
@ -2223,13 +2223,13 @@ static int cortex_a_write_apb_ab_memory(struct target *target,
return ERROR_OK;
/* Clear any abort. */
retval = mem_ap_sel_write_atomic_u32(armv7a->debug_ap,
retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DRCR, DRCR_CLEAR_EXCEPTIONS);
if (retval != ERROR_OK)
return retval;
/* Read DSCR. */
retval = mem_ap_sel_read_atomic_u32(armv7a->debug_ap,
retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DSCR, &dscr);
if (retval != ERROR_OK)
return retval;
@ -2248,7 +2248,7 @@ static int cortex_a_write_apb_ab_memory(struct target *target,
goto out;
/* Get the memory address into R0. */
retval = mem_ap_sel_write_atomic_u32(armv7a->debug_ap,
retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DTRRX, address);
if (retval != ERROR_OK)
goto out;
@ -2292,7 +2292,7 @@ out:
/* If there were any sticky abort flags, clear them. */
if (dscr & (DSCR_STICKY_ABORT_PRECISE | DSCR_STICKY_ABORT_IMPRECISE)) {
fault_dscr = dscr;
mem_ap_sel_write_atomic_u32(armv7a->debug_ap,
mem_ap_write_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DRCR, DRCR_CLEAR_EXCEPTIONS);
dscr &= ~(DSCR_STICKY_ABORT_PRECISE | DSCR_STICKY_ABORT_IMPRECISE);
} else {
@ -2326,7 +2326,7 @@ out:
/* If the DCC is nonempty, clear it. */
if (dscr & DSCR_DTRTX_FULL_LATCHED) {
uint32_t dummy;
retval = mem_ap_sel_read_atomic_u32(armv7a->debug_ap,
retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DTRTX, &dummy);
if (final_retval == ERROR_OK)
final_retval = retval;
@ -2398,7 +2398,7 @@ static int cortex_a_read_apb_ab_memory_slow(struct target *target,
return retval;
/* Read the value transferred to DTRTX into the buffer. */
retval = mem_ap_sel_read_atomic_u32(armv7a->debug_ap,
retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DTRTX, &data);
if (retval != ERROR_OK)
return retval;
@ -2450,7 +2450,7 @@ static int cortex_a_read_apb_ab_memory_fast(struct target *target,
return retval;
/* Latch LDC instruction. */
retval = mem_ap_sel_write_atomic_u32(armv7a->debug_ap,
retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_ITR, ARMV4_5_LDC(0, 1, 0, 1, 14, 5, 0, 4));
if (retval != ERROR_OK)
return retval;
@ -2461,7 +2461,7 @@ static int cortex_a_read_apb_ab_memory_fast(struct target *target,
* memory. The last read of DTRTX in this call reads the second-to-last
* word from memory and issues the read instruction for the last word.
*/
retval = mem_ap_sel_read_buf_noincr(armv7a->debug_ap, buffer,
retval = mem_ap_read_buf_noincr(armv7a->debug_ap, buffer,
4, count, armv7a->debug_base + CPUDBG_DTRTX);
if (retval != ERROR_OK)
return retval;
@ -2495,7 +2495,7 @@ static int cortex_a_read_apb_ab_memory_fast(struct target *target,
/* Read the value transferred to DTRTX into the buffer. This is the last
* word. */
retval = mem_ap_sel_read_atomic_u32(armv7a->debug_ap,
retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DTRTX, &u32);
if (retval != ERROR_OK)
return retval;
@ -2525,13 +2525,13 @@ static int cortex_a_read_apb_ab_memory(struct target *target,
return ERROR_OK;
/* Clear any abort. */
retval = mem_ap_sel_write_atomic_u32(armv7a->debug_ap,
retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DRCR, DRCR_CLEAR_EXCEPTIONS);
if (retval != ERROR_OK)
return retval;
/* Read DSCR */
retval = mem_ap_sel_read_atomic_u32(armv7a->debug_ap,
retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DSCR, &dscr);
if (retval != ERROR_OK)
return retval;
@ -2550,7 +2550,7 @@ static int cortex_a_read_apb_ab_memory(struct target *target,
goto out;
/* Get the memory address into R0. */
retval = mem_ap_sel_write_atomic_u32(armv7a->debug_ap,
retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DTRRX, address);
if (retval != ERROR_OK)
goto out;
@ -2582,7 +2582,7 @@ out:
/* If there were any sticky abort flags, clear them. */
if (dscr & (DSCR_STICKY_ABORT_PRECISE | DSCR_STICKY_ABORT_IMPRECISE)) {
fault_dscr = dscr;
mem_ap_sel_write_atomic_u32(armv7a->debug_ap,
mem_ap_write_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DRCR, DRCR_CLEAR_EXCEPTIONS);
dscr &= ~(DSCR_STICKY_ABORT_PRECISE | DSCR_STICKY_ABORT_IMPRECISE);
} else {
@ -2616,7 +2616,7 @@ out:
/* If the DCC is nonempty, clear it. */
if (dscr & DSCR_DTRTX_FULL_LATCHED) {
uint32_t dummy;
retval = mem_ap_sel_read_atomic_u32(armv7a->debug_ap,
retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DTRTX, &dummy);
if (final_retval == ERROR_OK)
final_retval = retval;
@ -2711,7 +2711,7 @@ static int cortex_a_read_memory_ahb(struct target *target, uint32_t address,
if (!count || !buffer)
return ERROR_COMMAND_SYNTAX_ERROR;
retval = mem_ap_sel_read_buf(armv7a->memory_ap, buffer, size, count, address);
retval = mem_ap_read_buf(armv7a->memory_ap, buffer, size, count, address);
return retval;
}
@ -2792,7 +2792,7 @@ static int cortex_a_write_memory_ahb(struct target *target, uint32_t address,
if (!count || !buffer)
return ERROR_COMMAND_SYNTAX_ERROR;
retval = mem_ap_sel_write_buf(armv7a->memory_ap, buffer, size, count, address);
retval = mem_ap_write_buf(armv7a->memory_ap, buffer, size, count, address);
return retval;
}
@ -2879,16 +2879,16 @@ static int cortex_a_handle_target_request(void *priv)
if (target->state == TARGET_RUNNING) {
uint32_t request;
uint32_t dscr;
retval = mem_ap_sel_read_atomic_u32(armv7a->debug_ap,
retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DSCR, &dscr);
/* check if we have data */
while ((dscr & DSCR_DTR_TX_FULL) && (retval == ERROR_OK)) {
retval = mem_ap_sel_read_atomic_u32(armv7a->debug_ap,
retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DTRTX, &request);
if (retval == ERROR_OK) {
target_request(target, request);
retval = mem_ap_sel_read_atomic_u32(armv7a->debug_ap,
retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DSCR, &dscr);
}
}
@ -2968,33 +2968,33 @@ static int cortex_a_examine_first(struct target *target)
} else
armv7a->debug_base = target->dbgbase;
retval = mem_ap_sel_read_atomic_u32(armv7a->debug_ap,
retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_CPUID, &cpuid);
if (retval != ERROR_OK)
return retval;
retval = mem_ap_sel_read_atomic_u32(armv7a->debug_ap,
retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_CPUID, &cpuid);
if (retval != ERROR_OK) {
LOG_DEBUG("Examine %s failed", "CPUID");
return retval;
}
retval = mem_ap_sel_read_atomic_u32(armv7a->debug_ap,
retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_CTYPR, &ctypr);
if (retval != ERROR_OK) {
LOG_DEBUG("Examine %s failed", "CTYPR");
return retval;
}
retval = mem_ap_sel_read_atomic_u32(armv7a->debug_ap,
retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_TTYPR, &ttypr);
if (retval != ERROR_OK) {
LOG_DEBUG("Examine %s failed", "TTYPR");
return retval;
}
retval = mem_ap_sel_read_atomic_u32(armv7a->debug_ap,
retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DIDR, &didr);
if (retval != ERROR_OK) {
LOG_DEBUG("Examine %s failed", "DIDR");
@ -3015,7 +3015,7 @@ static int cortex_a_examine_first(struct target *target)
if ((cpuid & CORTEX_A_MIDR_PARTNUM_MASK) >> CORTEX_A_MIDR_PARTNUM_SHIFT ==
CORTEX_A15_PARTNUM) {
retval = mem_ap_sel_write_atomic_u32(armv7a->debug_ap,
retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_OSLAR,
0);
@ -3027,7 +3027,7 @@ static int cortex_a_examine_first(struct target *target)
if ((cpuid & CORTEX_A_MIDR_PARTNUM_MASK) >> CORTEX_A_MIDR_PARTNUM_SHIFT ==
CORTEX_A7_PARTNUM) {
retval = mem_ap_sel_write_atomic_u32(armv7a->debug_ap,
retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_OSLAR,
0);
@ -3035,7 +3035,7 @@ static int cortex_a_examine_first(struct target *target)
return retval;
}
retval = mem_ap_sel_read_atomic_u32(armv7a->debug_ap,
retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_PRSR, &dbg_osreg);
if (retval != ERROR_OK)

104
src/target/cortex_m.c
View File

@ -73,16 +73,16 @@ static int cortexm_dap_read_coreregister_u32(struct target *target,
/* because the DCB_DCRDR is used for the emulated dcc channel
* we have to save/restore the DCB_DCRDR when used */
if (target->dbg_msg_enabled) {
retval = mem_ap_sel_read_u32(armv7m->debug_ap, DCB_DCRDR, &dcrdr);
retval = mem_ap_read_u32(armv7m->debug_ap, DCB_DCRDR, &dcrdr);
if (retval != ERROR_OK)
return retval;
}
retval = mem_ap_sel_write_u32(armv7m->debug_ap, DCB_DCRSR, regnum);
retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DCRSR, regnum);
if (retval != ERROR_OK)
return retval;
retval = mem_ap_sel_read_atomic_u32(armv7m->debug_ap, DCB_DCRDR, value);
retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DCRDR, value);
if (retval != ERROR_OK)
return retval;
@ -90,7 +90,7 @@ static int cortexm_dap_read_coreregister_u32(struct target *target,
/* restore DCB_DCRDR - this needs to be in a separate
* transaction otherwise the emulated DCC channel breaks */
if (retval == ERROR_OK)
retval = mem_ap_sel_write_atomic_u32(armv7m->debug_ap, DCB_DCRDR, dcrdr);
retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DCRDR, dcrdr);
}
return retval;
@ -106,16 +106,16 @@ static int cortexm_dap_write_coreregister_u32(struct target *target,
/* because the DCB_DCRDR is used for the emulated dcc channel
* we have to save/restore the DCB_DCRDR when used */
if (target->dbg_msg_enabled) {
retval = mem_ap_sel_read_u32(armv7m->debug_ap, DCB_DCRDR, &dcrdr);
retval = mem_ap_read_u32(armv7m->debug_ap, DCB_DCRDR, &dcrdr);
if (retval != ERROR_OK)
return retval;
}
retval = mem_ap_sel_write_u32(armv7m->debug_ap, DCB_DCRDR, value);
retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DCRDR, value);
if (retval != ERROR_OK)
return retval;
retval = mem_ap_sel_write_atomic_u32(armv7m->debug_ap, DCB_DCRSR, regnum | DCRSR_WnR);
retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DCRSR, regnum | DCRSR_WnR);
if (retval != ERROR_OK)
return retval;
@ -123,7 +123,7 @@ static int cortexm_dap_write_coreregister_u32(struct target *target,
/* restore DCB_DCRDR - this needs to be in a seperate
* transaction otherwise the emulated DCC channel breaks */
if (retval == ERROR_OK)
retval = mem_ap_sel_write_atomic_u32(armv7m->debug_ap, DCB_DCRDR, dcrdr);
retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DCRDR, dcrdr);
}
return retval;
@ -140,7 +140,7 @@ static int cortex_m_write_debug_halt_mask(struct target *target,
/* create new register mask */
cortex_m->dcb_dhcsr |= DBGKEY | C_DEBUGEN | mask_on;
return mem_ap_sel_write_atomic_u32(armv7m->debug_ap, DCB_DHCSR, cortex_m->dcb_dhcsr);
return mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DHCSR, cortex_m->dcb_dhcsr);
}
static int cortex_m_clear_halt(struct target *target)
@ -153,12 +153,12 @@ static int cortex_m_clear_halt(struct target *target)
cortex_m_write_debug_halt_mask(target, C_HALT, C_STEP);
/* Read Debug Fault Status Register */
retval = mem_ap_sel_read_atomic_u32(armv7m->debug_ap, NVIC_DFSR, &cortex_m->nvic_dfsr);
retval = mem_ap_read_atomic_u32(armv7m->debug_ap, NVIC_DFSR, &cortex_m->nvic_dfsr);
if (retval != ERROR_OK)
return retval;
/* Clear Debug Fault Status */
retval = mem_ap_sel_write_atomic_u32(armv7m->debug_ap, NVIC_DFSR, cortex_m->nvic_dfsr);
retval = mem_ap_write_atomic_u32(armv7m->debug_ap, NVIC_DFSR, cortex_m->nvic_dfsr);
if (retval != ERROR_OK)
return retval;
LOG_DEBUG(" NVIC_DFSR 0x%" PRIx32 "", cortex_m->nvic_dfsr);
@ -181,12 +181,12 @@ static int cortex_m_single_step_core(struct target *target)
* HALT can put the core into an unknown state.
*/
if (!(cortex_m->dcb_dhcsr & C_MASKINTS)) {
retval = mem_ap_sel_write_atomic_u32(armv7m->debug_ap, DCB_DHCSR,
retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DHCSR,
DBGKEY | C_MASKINTS | C_HALT | C_DEBUGEN);
if (retval != ERROR_OK)
return retval;
}
retval = mem_ap_sel_write_atomic_u32(armv7m->debug_ap, DCB_DHCSR,
retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DHCSR,
DBGKEY | C_MASKINTS | C_STEP | C_DEBUGEN);
if (retval != ERROR_OK)
return retval;
@ -229,22 +229,22 @@ static int cortex_m_endreset_event(struct target *target)
struct cortex_m_dwt_comparator *dwt_list = cortex_m->dwt_comparator_list;
/* REVISIT The four debug monitor bits are currently ignored... */
retval = mem_ap_sel_read_atomic_u32(armv7m->debug_ap, DCB_DEMCR, &dcb_demcr);
retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DEMCR, &dcb_demcr);
if (retval != ERROR_OK)
return retval;
LOG_DEBUG("DCB_DEMCR = 0x%8.8" PRIx32 "", dcb_demcr);
/* this register is used for emulated dcc channel */
retval = mem_ap_sel_write_u32(armv7m->debug_ap, DCB_DCRDR, 0);
retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DCRDR, 0);
if (retval != ERROR_OK)
return retval;
/* Enable debug requests */
retval = mem_ap_sel_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
if (retval != ERROR_OK)
return retval;
if (!(cortex_m->dcb_dhcsr & C_DEBUGEN)) {
retval = mem_ap_sel_write_u32(armv7m->debug_ap, DCB_DHCSR, DBGKEY | C_DEBUGEN);
retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DHCSR, DBGKEY | C_DEBUGEN);
if (retval != ERROR_OK)
return retval;
}
@ -259,7 +259,7 @@ static int cortex_m_endreset_event(struct target *target)
* choices *EXCEPT* explicitly scripted overrides like "vector_catch"
* or manual updates to the NVIC SHCSR and CCR registers.
*/
retval = mem_ap_sel_write_u32(armv7m->debug_ap, DCB_DEMCR, TRCENA | armv7m->demcr);
retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DEMCR, TRCENA | armv7m->demcr);
if (retval != ERROR_OK)
return retval;
@ -305,7 +305,7 @@ static int cortex_m_endreset_event(struct target *target)
register_cache_invalidate(armv7m->arm.core_cache);
/* make sure we have latest dhcsr flags */
retval = mem_ap_sel_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
return retval;
}
@ -341,47 +341,47 @@ static int cortex_m_examine_exception_reason(struct target *target)
struct adiv5_dap *swjdp = armv7m->arm.dap;
int retval;
retval = mem_ap_sel_read_u32(armv7m->debug_ap, NVIC_SHCSR, &shcsr);
retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_SHCSR, &shcsr);
if (retval != ERROR_OK)
return retval;
switch (armv7m->exception_number) {
case 2: /* NMI */
break;
case 3: /* Hard Fault */
retval = mem_ap_sel_read_atomic_u32(armv7m->debug_ap, NVIC_HFSR, &except_sr);
retval = mem_ap_read_atomic_u32(armv7m->debug_ap, NVIC_HFSR, &except_sr);
if (retval != ERROR_OK)
return retval;
if (except_sr & 0x40000000) {
retval = mem_ap_sel_read_u32(armv7m->debug_ap, NVIC_CFSR, &cfsr);
retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_CFSR, &cfsr);
if (retval != ERROR_OK)
return retval;
}
break;
case 4: /* Memory Management */
retval = mem_ap_sel_read_u32(armv7m->debug_ap, NVIC_CFSR, &except_sr);
retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_CFSR, &except_sr);
if (retval != ERROR_OK)
return retval;
retval = mem_ap_sel_read_u32(armv7m->debug_ap, NVIC_MMFAR, &except_ar);
retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_MMFAR, &except_ar);
if (retval != ERROR_OK)
return retval;
break;
case 5: /* Bus Fault */
retval = mem_ap_sel_read_u32(armv7m->debug_ap, NVIC_CFSR, &except_sr);
retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_CFSR, &except_sr);
if (retval != ERROR_OK)
return retval;
retval = mem_ap_sel_read_u32(armv7m->debug_ap, NVIC_BFAR, &except_ar);
retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_BFAR, &except_ar);
if (retval != ERROR_OK)
return retval;
break;
case 6: /* Usage Fault */
retval = mem_ap_sel_read_u32(armv7m->debug_ap, NVIC_CFSR, &except_sr);
retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_CFSR, &except_sr);
if (retval != ERROR_OK)
return retval;
break;
case 11: /* SVCall */
break;
case 12: /* Debug Monitor */
retval = mem_ap_sel_read_u32(armv7m->debug_ap, NVIC_DFSR, &except_sr);
retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_DFSR, &except_sr);
if (retval != ERROR_OK)
return retval;
break;
@ -415,7 +415,7 @@ static int cortex_m_debug_entry(struct target *target)
LOG_DEBUG(" ");
cortex_m_clear_halt(target);
retval = mem_ap_sel_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
if (retval != ERROR_OK)
return retval;
@ -492,7 +492,7 @@ static int cortex_m_poll(struct target *target)
struct armv7m_common *armv7m = &cortex_m->armv7m;
/* Read from Debug Halting Control and Status Register */
retval = mem_ap_sel_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
if (retval != ERROR_OK) {
target->state = TARGET_UNKNOWN;
return retval;
@ -513,7 +513,7 @@ static int cortex_m_poll(struct target *target)
detected_failure = ERROR_FAIL;
/* refresh status bits */
retval = mem_ap_sel_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
if (retval != ERROR_OK)
return retval;
}
@ -628,13 +628,13 @@ static int cortex_m_soft_reset_halt(struct target *target)
LOG_WARNING("soft_reset_halt is deprecated, please use 'reset halt' instead.");
/* Enter debug state on reset; restore DEMCR in endreset_event() */
retval = mem_ap_sel_write_u32(armv7m->debug_ap, DCB_DEMCR,
retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DEMCR,
TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
if (retval != ERROR_OK)
return retval;
/* Request a core-only reset */
retval = mem_ap_sel_write_atomic_u32(armv7m->debug_ap, NVIC_AIRCR,
retval = mem_ap_write_atomic_u32(armv7m->debug_ap, NVIC_AIRCR,
AIRCR_VECTKEY | AIRCR_VECTRESET);
if (retval != ERROR_OK)
return retval;
@ -644,9 +644,9 @@ static int cortex_m_soft_reset_halt(struct target *target)
register_cache_invalidate(cortex_m->armv7m.arm.core_cache);
while (timeout < 100) {
retval = mem_ap_sel_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &dcb_dhcsr);
retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &dcb_dhcsr);
if (retval == ERROR_OK) {
retval = mem_ap_sel_read_atomic_u32(armv7m->debug_ap, NVIC_DFSR,
retval = mem_ap_read_atomic_u32(armv7m->debug_ap, NVIC_DFSR,
&cortex_m->nvic_dfsr);
if (retval != ERROR_OK)
return retval;
@ -889,7 +889,7 @@ static int cortex_m_step(struct target *target, int current,
/* Wait for pending handlers to complete or timeout */
do {
retval = mem_ap_sel_read_atomic_u32(armv7m->debug_ap,
retval = mem_ap_read_atomic_u32(armv7m->debug_ap,
DCB_DHCSR,
&cortex_m->dcb_dhcsr);
if (retval != ERROR_OK) {
@ -924,7 +924,7 @@ static int cortex_m_step(struct target *target, int current,
}
}
retval = mem_ap_sel_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
if (retval != ERROR_OK)
return retval;
@ -991,11 +991,11 @@ static int cortex_m_assert_reset(struct target *target)
/* Enable debug requests */
int retval;
retval = mem_ap_sel_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
if (retval != ERROR_OK)
return retval;
if (!(cortex_m->dcb_dhcsr & C_DEBUGEN)) {
retval = mem_ap_sel_write_u32(armv7m->debug_ap, DCB_DHCSR, DBGKEY | C_DEBUGEN);
retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DHCSR, DBGKEY | C_DEBUGEN);
if (retval != ERROR_OK)
return retval;
}
@ -1003,19 +1003,19 @@ static int cortex_m_assert_reset(struct target *target)
/* If the processor is sleeping in a WFI or WFE instruction, the
* C_HALT bit must be asserted to regain control */
if (cortex_m->dcb_dhcsr & S_SLEEP) {
retval = mem_ap_sel_write_u32(armv7m->debug_ap, DCB_DHCSR, DBGKEY | C_HALT | C_DEBUGEN);
retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DHCSR, DBGKEY | C_HALT | C_DEBUGEN);
if (retval != ERROR_OK)
return retval;
}
retval = mem_ap_sel_write_u32(armv7m->debug_ap, DCB_DCRDR, 0);
retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DCRDR, 0);
if (retval != ERROR_OK)
return retval;
if (!target->reset_halt) {
/* Set/Clear C_MASKINTS in a separate operation */
if (cortex_m->dcb_dhcsr & C_MASKINTS) {
retval = mem_ap_sel_write_atomic_u32(armv7m->debug_ap, DCB_DHCSR,
retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DHCSR,
DBGKEY | C_DEBUGEN | C_HALT);
if (retval != ERROR_OK)
return retval;
@ -1033,7 +1033,7 @@ static int cortex_m_assert_reset(struct target *target)
* bad vector table entries. Should this include MMERR or
* other flags too?
*/
retval = mem_ap_sel_write_atomic_u32(armv7m->debug_ap, DCB_DEMCR,
retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DEMCR,
TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
if (retval != ERROR_OK)
return retval;
@ -1057,7 +1057,7 @@ static int cortex_m_assert_reset(struct target *target)
"handler to reset any peripherals or configure hardware srst support.");
}
retval = mem_ap_sel_write_atomic_u32(armv7m->debug_ap, NVIC_AIRCR,
retval = mem_ap_write_atomic_u32(armv7m->debug_ap, NVIC_AIRCR,
AIRCR_VECTKEY | ((reset_config == CORTEX_M_RESET_SYSRESETREQ)
? AIRCR_SYSRESETREQ : AIRCR_VECTRESET));
if (retval != ERROR_OK)
@ -1075,7 +1075,7 @@ static int cortex_m_assert_reset(struct target *target)
* after reset) on LM3S6918 -- Michael Schwingen
*/
uint32_t tmp;
retval = mem_ap_sel_read_atomic_u32(armv7m->debug_ap, NVIC_AIRCR, &tmp);
retval = mem_ap_read_atomic_u32(armv7m->debug_ap, NVIC_AIRCR, &tmp);
if (retval != ERROR_OK)
return retval;
}
@ -1669,7 +1669,7 @@ static int cortex_m_read_memory(struct target *target, uint32_t address,
return ERROR_TARGET_UNALIGNED_ACCESS;
}
return mem_ap_sel_read_buf(armv7m->debug_ap, buffer, size, count, address);
return mem_ap_read_buf(armv7m->debug_ap, buffer, size, count, address);
}
static int cortex_m_write_memory(struct target *target, uint32_t address,
@ -1683,7 +1683,7 @@ static int cortex_m_write_memory(struct target *target, uint32_t address,
return ERROR_TARGET_UNALIGNED_ACCESS;
}
return mem_ap_sel_write_buf(armv7m->debug_ap, buffer, size, count, address);
return mem_ap_write_buf(armv7m->debug_ap, buffer, size, count, address);
}
static int cortex_m_init_target(struct command_context *cmd_ctx,
@ -2025,7 +2025,7 @@ static int cortex_m_dcc_read(struct target *target, uint8_t *value, uint8_t *ctr
uint8_t buf[2];
int retval;
retval = mem_ap_sel_read_buf_noincr(armv7m->debug_ap, buf, 2, 1, DCB_DCRDR);
retval = mem_ap_read_buf_noincr(armv7m->debug_ap, buf, 2, 1, DCB_DCRDR);
if (retval != ERROR_OK)
return retval;
@ -2039,7 +2039,7 @@ static int cortex_m_dcc_read(struct target *target, uint8_t *value, uint8_t *ctr
* signify we have read data */
if (dcrdr & (1 << 0)) {
target_buffer_set_u16(target, buf, 0);
retval = mem_ap_sel_write_buf_noincr(armv7m->debug_ap, buf, 2, 1, DCB_DCRDR);
retval = mem_ap_write_buf_noincr(armv7m->debug_ap, buf, 2, 1, DCB_DCRDR);
if (retval != ERROR_OK)
return retval;
}
@ -2194,7 +2194,7 @@ COMMAND_HANDLER(handle_cortex_m_vector_catch_command)
if (retval != ERROR_OK)
return retval;
retval = mem_ap_sel_read_atomic_u32(armv7m->debug_ap, DCB_DEMCR, &demcr);
retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DEMCR, &demcr);
if (retval != ERROR_OK)
return retval;
@ -2231,10 +2231,10 @@ write:
demcr |= catch;
/* write, but don't assume it stuck (why not??) */
retval = mem_ap_sel_write_u32(armv7m->debug_ap, DCB_DEMCR, demcr);
retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DEMCR, demcr);
if (retval != ERROR_OK)
return retval;
retval = mem_ap_sel_read_atomic_u32(armv7m->debug_ap, DCB_DEMCR, &demcr);
retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DEMCR, &demcr);
if (retval != ERROR_OK)
return retval;