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Merge pull request #281 from riscv/docs 

Explain what RISC-V targets are supported.
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Tim Newsome 2018-07-17 15:03:35 -07:00 committed by GitHub
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@ -8903,8 +8903,11 @@ Display all registers in @emph{group}.
@section RISC-V Architecture
@uref{http://riscv.org/, RISC-V} is a free and open ISA. OpenOCD supports JTAG
debug of targets that implement version 0.11 and 0.13 of the RISC-V Debug
Specification.
debug of RV32 and RV64 cores in heterogeneous multicore systems of up to 32
harts. (It's possible to increase this limit to 1024 by changing
RISCV_MAX_HARTS in riscv.h.) OpenOCD primarily supports 0.13 of the RISC-V
Debug Specification, but there is also support for legacy targets that
implement version 0.11.
@subsection RISC-V Terminology