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Merge pull request #230 from riscv/deleg 

Make m*deleg regs conditional on U/S/N
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Tim Newsome 2018-03-30 14:02:13 -07:00 committed by GitHub
parent 358a85baf4 224e7b4f16
commit 3c7c7e26a4
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1 changed files with 8 additions and 0 deletions
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8
src/target/riscv/riscv.c
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@ -2343,6 +2343,14 @@ int riscv_init_registers(struct target *target)
case CSR_SATP: case CSR_SATP:
r->exist = riscv_supports_extension(target, 'S'); r->exist = riscv_supports_extension(target, 'S');
break; break;
case CSR_MEDELEG:
case CSR_MIDELEG:
/* "In systems with only M-mode, or with both M-mode and
* U-mode but without U-mode trap support, the medeleg and
* mideleg registers should not exist." */
r->exist = riscv_supports_extension(target, 'S') ||
riscv_supports_extension(target, 'N');
break;
} }
if (!r->exist && expose_csr) { if (!r->exist && expose_csr) {