From b6dca68b2e03a1344007939702f1a84faa56343d Mon Sep 17 00:00:00 2001 From: Tim Newsome Date: Fri, 23 Mar 2018 13:43:12 -0700 Subject: [PATCH 1/3] Make m*deleg regs conditional on U/S/N Change-Id: I544fc15625400d8ad64d4a65f0fc9d77f428ca84 --- src/target/riscv/riscv.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/src/target/riscv/riscv.c b/src/target/riscv/riscv.c index 9f16a400a..073a355e1 100644 --- a/src/target/riscv/riscv.c +++ b/src/target/riscv/riscv.c @@ -2323,6 +2323,15 @@ int riscv_init_registers(struct target *target) case CSR_SATP: r->exist = riscv_supports_extension(target, 'S'); break; + case CSR_MEDELEG: + case CSR_MIDELEG: + /* "In systems with only M-mode, or with both M-mode and + * U-mode but without U-mode trap support, the medeleg and + * mideleg registers should not exist." */ + r->exist = (riscv_supports_extension(target, 'S') || + riscv_supports_extension(target, 'U')) && + !riscv_supports_extension(target, 'N'); + break; } if (!r->exist && expose_csr) { From 0c05aafbf83cf38167aae83c6622d3ecb4b80f44 Mon Sep 17 00:00:00 2001 From: Tim Newsome Date: Mon, 26 Mar 2018 16:00:34 -0700 Subject: [PATCH 2/3] Fix m*deleg logic. Change-Id: Ieda035280334f8e7dc78c9fbc2bdbea7c565d2de --- src/target/riscv/riscv.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/target/riscv/riscv.c b/src/target/riscv/riscv.c index 073a355e1..89c0dc7e0 100644 --- a/src/target/riscv/riscv.c +++ b/src/target/riscv/riscv.c @@ -2328,8 +2328,7 @@ int riscv_init_registers(struct target *target) /* "In systems with only M-mode, or with both M-mode and * U-mode but without U-mode trap support, the medeleg and * mideleg registers should not exist." */ - r->exist = (riscv_supports_extension(target, 'S') || - riscv_supports_extension(target, 'U')) && + r->exist = riscv_supports_extension(target, 'S') || !riscv_supports_extension(target, 'N'); break; } From 224e7b4f16784d7872ca42125a66d6266d237668 Mon Sep 17 00:00:00 2001 From: Tim Newsome Date: Tue, 27 Mar 2018 11:42:32 -0700 Subject: [PATCH 3/3] Once more... Less sloppy this time. Change-Id: I4a24e777af3a0d8e072bc1bce0b314738393aa86 --- src/target/riscv/riscv.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/target/riscv/riscv.c b/src/target/riscv/riscv.c index 89c0dc7e0..8c18ff7e7 100644 --- a/src/target/riscv/riscv.c +++ b/src/target/riscv/riscv.c @@ -2329,7 +2329,7 @@ int riscv_init_registers(struct target *target) * U-mode but without U-mode trap support, the medeleg and * mideleg registers should not exist." */ r->exist = riscv_supports_extension(target, 'S') || - !riscv_supports_extension(target, 'N'); + riscv_supports_extension(target, 'N'); break; }