interesting
/
riscv-openocd
mirror of https://github.com/riscv/riscv-openocd.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

moves handling of problems with resetting into the halted state 

into the target implementation.

Also target_process_reset() is now simpler and has error handling,
e.g. if assert reset fails, then target_process_reset() will propagate
that error.

cmd_ctx was passed in to examine(), which is wrong - removed that.

git-svn-id: svn://svn.berlios.de/openocd/trunk@887 b42882b7-edfa-0310-969c-e2dbd0fdcd60
This commit is contained in:
oharboe 2008-08-05 06:18:26 +00:00
parent e4729b3b7a
commit 3a48961820
12 changed files with 54 additions and 48 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/target/arm11.c
View File

@ -1378,7 +1378,7 @@ int arm11_init_target(struct command_context_s *cmd_ctx, struct target_s *target
}
/* talk to the target and set things up */
int arm11_examine(struct command_context_s *cmd_ctx, struct target_s *target)
int arm11_examine(struct target_s *target)
{
FNC_INFO;

2
src/target/arm11.h
View File

@ -188,7 +188,7 @@ int arm11_target_request_data(struct target_s *target, u32 size, u8 *buffer);
int arm11_halt(struct target_s *target);
int arm11_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution);
int arm11_step(struct target_s *target, int current, u32 address, int handle_breakpoints);
int arm11_examine(struct command_context_s *cmd_ctx, struct target_s *target);
int arm11_examine(struct target_s *target);
/* target reset control */
int arm11_assert_reset(struct target_s *target);

22
src/target/arm7_9_common.c
View File

@ -821,12 +821,26 @@ int arm7_9_assert_reset(target_t *target)
int arm7_9_deassert_reset(target_t *target)
{
int retval=ERROR_OK;
LOG_DEBUG("target->state: %s", target_state_strings[target->state]);
/* deassert reset lines */
jtag_add_reset(0, 0);
return ERROR_OK;
if ((jtag_reset_config & RESET_SRST_PULLS_TRST)!=0)
{
/* set up embedded ice registers again */
if ((retval=target->type->examine(target))!=ERROR_OK)
return retval;
if (target->reset_halt)
{
/* halt the CPU as embedded ice was not set up in reset */
if ((retval=target->type->halt(target))!=ERROR_OK)
return retval;
}
}
return retval;
}
int arm7_9_clear_halt(target_t *target)
@ -961,6 +975,12 @@ int arm7_9_soft_reset_halt(struct target_s *target)
int arm7_9_halt(target_t *target)
{
if ((target->state==TARGET_RESET)&&((jtag_reset_config & RESET_SRST_PULLS_TRST)!=0))
{
LOG_WARNING("arm7/9 can't halt a target in reset if srst pulls trst - halting after reset");
return ERROR_OK;
}
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];

2
src/target/arm7tdmi.c
View File

@ -708,7 +708,7 @@ void arm7tdmi_build_reg_cache(target_t *target)
armv4_5->core_cache = (*cache_p);
}
int arm7tdmi_examine(struct command_context_s *cmd_ctx, struct target_s *target)
int arm7tdmi_examine(struct target_s *target)
{
int retval;
armv4_5_common_t *armv4_5 = target->arch_info;

2
src/target/arm7tdmi.h
View File

@ -40,7 +40,7 @@ typedef struct arm7tdmi_common_s
int arm7tdmi_register_commands(struct command_context_s *cmd_ctx);
int arm7tdmi_init_arch_info(target_t *target, arm7tdmi_common_t *arm7tdmi, int chain_pos, char *variant);
int arm7tdmi_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
int arm7tdmi_examine(struct command_context_s *cmd_ctx, struct target_s *target);
int arm7tdmi_examine(struct target_s *target);
#endif /* ARM7TDMI_H */

2
src/target/arm9tdmi.c
View File

@ -850,7 +850,7 @@ void arm9tdmi_build_reg_cache(target_t *target)
}
int arm9tdmi_examine(struct command_context_s *cmd_ctx, struct target_s *target)
int arm9tdmi_examine(struct target_s *target)
{
/* get pointers to arch-specific information */
int retval;

2
src/target/arm9tdmi.h
View File

@ -56,7 +56,7 @@ enum arm9tdmi_vector
};
extern int arm9tdmi_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
int arm9tdmi_examine(struct command_context_s *cmd_ctx, struct target_s *target);
int arm9tdmi_examine(struct target_s *target);
extern int arm9tdmi_init_arch_info(target_t *target, arm9tdmi_common_t *arm9tdmi, int chain_pos, char *variant);
extern int arm9tdmi_register_commands(struct command_context_s *cmd_ctx);

4
src/target/cortex_m3.c
View File

@ -51,7 +51,7 @@ int cortex_m3_quit();
int cortex_m3_load_core_reg_u32(target_t *target, enum armv7m_regtype type, u32 num, u32 *value);
int cortex_m3_store_core_reg_u32(target_t *target, enum armv7m_regtype type, u32 num, u32 value);
int cortex_m3_target_request_data(target_t *target, u32 size, u8 *buffer);
int cortex_m3_examine(struct command_context_s *cmd_ctx, struct target_s *target);
int cortex_m3_examine(struct target_s *target);
#ifdef ARMV7_GDB_HACKS
extern u8 armv7m_gdb_dummy_cpsr_value[];
@ -1307,7 +1307,7 @@ int cortex_m3_init_target(struct command_context_s *cmd_ctx, struct target_s *ta
return ERROR_OK;
}
int cortex_m3_examine(struct command_context_s *cmd_ctx, struct target_s *target)
int cortex_m3_examine(struct target_s *target)
{
int retval;
u32 cpuid, fpcr, dwtcr, ictr;

6
src/target/feroceon.c
View File

@ -54,7 +54,7 @@
#include <stdlib.h>
#include <string.h>
int feroceon_examine(struct command_context_s *cmd_ctx, struct target_s *target);
int feroceon_examine(struct target_s *target);
int feroceon_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target);
int feroceon_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffer);
int feroceon_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
@ -694,13 +694,13 @@ int feroceon_target_command(struct command_context_s *cmd_ctx, char *cmd, char *
}
int feroceon_examine(struct command_context_s *cmd_ctx, struct target_s *target)
int feroceon_examine(struct target_s *target)
{
armv4_5_common_t *armv4_5;
arm7_9_common_t *arm7_9;
int retval;
retval = arm9tdmi_examine(cmd_ctx, target);
retval = arm9tdmi_examine(target);
if (retval!=ERROR_OK)
return retval;

4
src/target/mips_m4k.c
View File

@ -46,7 +46,7 @@ int mips_m4k_init_target(struct command_context_s *cmd_ctx, struct target_s *tar
int mips_m4k_quit();
int mips_m4k_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target);
int mips_m4k_examine(struct command_context_s *cmd_ctx, struct target_s *target);
int mips_m4k_examine(struct target_s *target);
int mips_m4k_assert_reset(target_t *target);
int mips_m4k_deassert_reset(target_t *target);
@ -610,7 +610,7 @@ int mips_m4k_target_command(struct command_context_s *cmd_ctx, char *cmd, char *
return ERROR_OK;
}
int mips_m4k_examine(struct command_context_s *cmd_ctx, struct target_s *target)
int mips_m4k_examine(struct target_s *target)
{
int retval;
mips32_common_t *mips32 = target->arch_info;

50
src/target/target.c
View File

@ -290,7 +290,7 @@ int target_process_reset(struct command_context_s *cmd_ctx, enum target_reset_mo
*
* For the "reset halt/init" case we must only set up the registers here.
*/
if ((retval = target_examine(cmd_ctx)) != ERROR_OK)
if ((retval = target_examine()) != ERROR_OK)
return retval;
keep_alive(); /* we might be running on a very slow JTAG clk */
@ -303,14 +303,10 @@ int target_process_reset(struct command_context_s *cmd_ctx, enum target_reset_mo
*/
target_free_all_working_areas_restore(target, 0);
target->reset_halt=((reset_mode==RESET_HALT)||(reset_mode==RESET_INIT));
target->type->assert_reset(target);
if ((retval = target->type->assert_reset(target))!=ERROR_OK)
return retval;
target = target->next;
}
if ((retval = jtag_execute_queue()) != ERROR_OK)
{
LOG_WARNING("JTAG communication failed asserting reset.");
retval = ERROR_OK;
}
/* request target halt if necessary, and schedule further action */
target = targets;
@ -318,23 +314,24 @@ int target_process_reset(struct command_context_s *cmd_ctx, enum target_reset_mo
{
if (reset_mode!=RESET_RUN)
{
if ((jtag_reset_config & RESET_SRST_PULLS_TRST)==0)
target_halt(target);
if ((retval = target_halt(target))!=ERROR_OK)
return retval;
}
target = target->next;
}
if ((retval = jtag_execute_queue()) != ERROR_OK)
{
LOG_WARNING("JTAG communication failed while reset was asserted. Consider using srst_only for reset_config.");
retval = ERROR_OK;
}
target = targets;
while (target)
{
target->type->deassert_reset(target);
/* We can fail to bring the target into the halted state */
if ((retval = target->type->deassert_reset(target))!=ERROR_OK)
return retval;
target = target->next;
}
target = targets;
while (target)
{
/* We can fail to bring the target into the halted state, try after reset has been deasserted */
if (target->reset_halt)
{
/* wait up to 1 second for halt. */
@ -342,25 +339,14 @@ int target_process_reset(struct command_context_s *cmd_ctx, enum target_reset_mo
if (target->state != TARGET_HALTED)
{
LOG_WARNING("Failed to reset target into halted mode - issuing halt");
target->type->halt(target);
if ((retval = target->type->halt(target))!=ERROR_OK)
return retval;
}
}
target = target->next;
}
if ((retval = jtag_execute_queue()) != ERROR_OK)
{
LOG_WARNING("JTAG communication failed while deasserting reset.");
retval = ERROR_OK;
}
if (jtag_reset_config & RESET_SRST_PULLS_TRST)
{
/* If TRST was asserted we need to set up registers again */
if ((retval = target_examine(cmd_ctx)) != ERROR_OK)
return retval;
}
LOG_DEBUG("Waiting for halted stated as appropriate");
@ -397,7 +383,7 @@ static int default_mmu(struct target_s *target, int *enabled)
return ERROR_OK;
}
static int default_examine(struct command_context_s *cmd_ctx, struct target_s *target)
static int default_examine(struct target_s *target)
{
target->type->examined = 1;
return ERROR_OK;
@ -415,7 +401,7 @@ int target_examine(struct command_context_s *cmd_ctx)
target_t *target = targets;
while (target)
{
if ((retval = target->type->examine(cmd_ctx, target))!=ERROR_OK)
if ((retval = target->type->examine(target))!=ERROR_OK)
return retval;
target = target->next;
}

4
src/target/target.h
View File

@ -182,7 +182,7 @@ typedef struct target_type_s
*
* invoked every time after the jtag chain has been validated/examined
*/
int (*examine)(struct command_context_s *cmd_ctx, struct target_s *target);
int (*examine)(struct target_s *target);
/* Set up structures for target.
*
* It is illegal to talk to the target at this stage as this fn is invoked
@ -250,7 +250,7 @@ typedef struct target_timer_callback_s
extern int target_register_commands(struct command_context_s *cmd_ctx);
extern int target_register_user_commands(struct command_context_s *cmd_ctx);
extern int target_init(struct command_context_s *cmd_ctx);
extern int target_examine(struct command_context_s *cmd_ctx);
extern int target_examine();
extern int handle_target(void *priv);
extern int target_process_reset(struct command_context_s *cmd_ctx, enum target_reset_mode reset_mode);