From 3a4896182036eb472a06f66be3710d5c228b6748 Mon Sep 17 00:00:00 2001 From: oharboe Date: Tue, 5 Aug 2008 06:18:26 +0000 Subject: [PATCH] moves handling of problems with resetting into the halted state into the target implementation. Also target_process_reset() is now simpler and has error handling, e.g. if assert reset fails, then target_process_reset() will propagate that error. cmd_ctx was passed in to examine(), which is wrong - removed that. git-svn-id: svn://svn.berlios.de/openocd/trunk@887 b42882b7-edfa-0310-969c-e2dbd0fdcd60 --- src/target/arm11.c | 2 +- src/target/arm11.h | 2 +- src/target/arm7_9_common.c | 22 ++++++++++++++++- src/target/arm7tdmi.c | 2 +- src/target/arm7tdmi.h | 2 +- src/target/arm9tdmi.c | 2 +- src/target/arm9tdmi.h | 2 +- src/target/cortex_m3.c | 4 +-- src/target/feroceon.c | 6 ++--- src/target/mips_m4k.c | 4 +-- src/target/target.c | 50 ++++++++++++++------------------------ src/target/target.h | 4 +-- 12 files changed, 54 insertions(+), 48 deletions(-) diff --git a/src/target/arm11.c b/src/target/arm11.c index da779b08e..11f6d9cc4 100644 --- a/src/target/arm11.c +++ b/src/target/arm11.c @@ -1378,7 +1378,7 @@ int arm11_init_target(struct command_context_s *cmd_ctx, struct target_s *target } /* talk to the target and set things up */ -int arm11_examine(struct command_context_s *cmd_ctx, struct target_s *target) +int arm11_examine(struct target_s *target) { FNC_INFO; diff --git a/src/target/arm11.h b/src/target/arm11.h index 8b05b2e1c..ccc9c09fc 100644 --- a/src/target/arm11.h +++ b/src/target/arm11.h @@ -188,7 +188,7 @@ int arm11_target_request_data(struct target_s *target, u32 size, u8 *buffer); int arm11_halt(struct target_s *target); int arm11_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution); int arm11_step(struct target_s *target, int current, u32 address, int handle_breakpoints); -int arm11_examine(struct command_context_s *cmd_ctx, struct target_s *target); +int arm11_examine(struct target_s *target); /* target reset control */ int arm11_assert_reset(struct target_s *target); diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c index 0531cad6c..117e9cb1d 100644 --- a/src/target/arm7_9_common.c +++ b/src/target/arm7_9_common.c @@ -821,12 +821,26 @@ int arm7_9_assert_reset(target_t *target) int arm7_9_deassert_reset(target_t *target) { + int retval=ERROR_OK; LOG_DEBUG("target->state: %s", target_state_strings[target->state]); /* deassert reset lines */ jtag_add_reset(0, 0); - return ERROR_OK; + if ((jtag_reset_config & RESET_SRST_PULLS_TRST)!=0) + { + /* set up embedded ice registers again */ + if ((retval=target->type->examine(target))!=ERROR_OK) + return retval; + + if (target->reset_halt) + { + /* halt the CPU as embedded ice was not set up in reset */ + if ((retval=target->type->halt(target))!=ERROR_OK) + return retval; + } + } + return retval; } int arm7_9_clear_halt(target_t *target) @@ -961,6 +975,12 @@ int arm7_9_soft_reset_halt(struct target_s *target) int arm7_9_halt(target_t *target) { + if ((target->state==TARGET_RESET)&&((jtag_reset_config & RESET_SRST_PULLS_TRST)!=0)) + { + LOG_WARNING("arm7/9 can't halt a target in reset if srst pulls trst - halting after reset"); + return ERROR_OK; + } + armv4_5_common_t *armv4_5 = target->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info; reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]; diff --git a/src/target/arm7tdmi.c b/src/target/arm7tdmi.c index ff398887d..41771ab18 100644 --- a/src/target/arm7tdmi.c +++ b/src/target/arm7tdmi.c @@ -708,7 +708,7 @@ void arm7tdmi_build_reg_cache(target_t *target) armv4_5->core_cache = (*cache_p); } -int arm7tdmi_examine(struct command_context_s *cmd_ctx, struct target_s *target) +int arm7tdmi_examine(struct target_s *target) { int retval; armv4_5_common_t *armv4_5 = target->arch_info; diff --git a/src/target/arm7tdmi.h b/src/target/arm7tdmi.h index 95b79385a..a9b41da2f 100644 --- a/src/target/arm7tdmi.h +++ b/src/target/arm7tdmi.h @@ -40,7 +40,7 @@ typedef struct arm7tdmi_common_s int arm7tdmi_register_commands(struct command_context_s *cmd_ctx); int arm7tdmi_init_arch_info(target_t *target, arm7tdmi_common_t *arm7tdmi, int chain_pos, char *variant); int arm7tdmi_init_target(struct command_context_s *cmd_ctx, struct target_s *target); -int arm7tdmi_examine(struct command_context_s *cmd_ctx, struct target_s *target); +int arm7tdmi_examine(struct target_s *target); #endif /* ARM7TDMI_H */ diff --git a/src/target/arm9tdmi.c b/src/target/arm9tdmi.c index a4d18dd57..adb21f79b 100644 --- a/src/target/arm9tdmi.c +++ b/src/target/arm9tdmi.c @@ -850,7 +850,7 @@ void arm9tdmi_build_reg_cache(target_t *target) } -int arm9tdmi_examine(struct command_context_s *cmd_ctx, struct target_s *target) +int arm9tdmi_examine(struct target_s *target) { /* get pointers to arch-specific information */ int retval; diff --git a/src/target/arm9tdmi.h b/src/target/arm9tdmi.h index 965679253..249a92874 100644 --- a/src/target/arm9tdmi.h +++ b/src/target/arm9tdmi.h @@ -56,7 +56,7 @@ enum arm9tdmi_vector }; extern int arm9tdmi_init_target(struct command_context_s *cmd_ctx, struct target_s *target); -int arm9tdmi_examine(struct command_context_s *cmd_ctx, struct target_s *target); +int arm9tdmi_examine(struct target_s *target); extern int arm9tdmi_init_arch_info(target_t *target, arm9tdmi_common_t *arm9tdmi, int chain_pos, char *variant); extern int arm9tdmi_register_commands(struct command_context_s *cmd_ctx); diff --git a/src/target/cortex_m3.c b/src/target/cortex_m3.c index e3ed4cfbb..e305c0189 100644 --- a/src/target/cortex_m3.c +++ b/src/target/cortex_m3.c @@ -51,7 +51,7 @@ int cortex_m3_quit(); int cortex_m3_load_core_reg_u32(target_t *target, enum armv7m_regtype type, u32 num, u32 *value); int cortex_m3_store_core_reg_u32(target_t *target, enum armv7m_regtype type, u32 num, u32 value); int cortex_m3_target_request_data(target_t *target, u32 size, u8 *buffer); -int cortex_m3_examine(struct command_context_s *cmd_ctx, struct target_s *target); +int cortex_m3_examine(struct target_s *target); #ifdef ARMV7_GDB_HACKS extern u8 armv7m_gdb_dummy_cpsr_value[]; @@ -1307,7 +1307,7 @@ int cortex_m3_init_target(struct command_context_s *cmd_ctx, struct target_s *ta return ERROR_OK; } -int cortex_m3_examine(struct command_context_s *cmd_ctx, struct target_s *target) +int cortex_m3_examine(struct target_s *target) { int retval; u32 cpuid, fpcr, dwtcr, ictr; diff --git a/src/target/feroceon.c b/src/target/feroceon.c index c87320ae8..8178e556b 100644 --- a/src/target/feroceon.c +++ b/src/target/feroceon.c @@ -54,7 +54,7 @@ #include #include -int feroceon_examine(struct command_context_s *cmd_ctx, struct target_s *target); +int feroceon_examine(struct target_s *target); int feroceon_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target); int feroceon_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffer); int feroceon_init_target(struct command_context_s *cmd_ctx, struct target_s *target); @@ -694,13 +694,13 @@ int feroceon_target_command(struct command_context_s *cmd_ctx, char *cmd, char * } -int feroceon_examine(struct command_context_s *cmd_ctx, struct target_s *target) +int feroceon_examine(struct target_s *target) { armv4_5_common_t *armv4_5; arm7_9_common_t *arm7_9; int retval; - retval = arm9tdmi_examine(cmd_ctx, target); + retval = arm9tdmi_examine(target); if (retval!=ERROR_OK) return retval; diff --git a/src/target/mips_m4k.c b/src/target/mips_m4k.c index 8695a6269..e89ee844c 100644 --- a/src/target/mips_m4k.c +++ b/src/target/mips_m4k.c @@ -46,7 +46,7 @@ int mips_m4k_init_target(struct command_context_s *cmd_ctx, struct target_s *tar int mips_m4k_quit(); int mips_m4k_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target); -int mips_m4k_examine(struct command_context_s *cmd_ctx, struct target_s *target); +int mips_m4k_examine(struct target_s *target); int mips_m4k_assert_reset(target_t *target); int mips_m4k_deassert_reset(target_t *target); @@ -610,7 +610,7 @@ int mips_m4k_target_command(struct command_context_s *cmd_ctx, char *cmd, char * return ERROR_OK; } -int mips_m4k_examine(struct command_context_s *cmd_ctx, struct target_s *target) +int mips_m4k_examine(struct target_s *target) { int retval; mips32_common_t *mips32 = target->arch_info; diff --git a/src/target/target.c b/src/target/target.c index 02016e774..5bd16622f 100644 --- a/src/target/target.c +++ b/src/target/target.c @@ -290,7 +290,7 @@ int target_process_reset(struct command_context_s *cmd_ctx, enum target_reset_mo * * For the "reset halt/init" case we must only set up the registers here. */ - if ((retval = target_examine(cmd_ctx)) != ERROR_OK) + if ((retval = target_examine()) != ERROR_OK) return retval; keep_alive(); /* we might be running on a very slow JTAG clk */ @@ -303,14 +303,10 @@ int target_process_reset(struct command_context_s *cmd_ctx, enum target_reset_mo */ target_free_all_working_areas_restore(target, 0); target->reset_halt=((reset_mode==RESET_HALT)||(reset_mode==RESET_INIT)); - target->type->assert_reset(target); + if ((retval = target->type->assert_reset(target))!=ERROR_OK) + return retval; target = target->next; } - if ((retval = jtag_execute_queue()) != ERROR_OK) - { - LOG_WARNING("JTAG communication failed asserting reset."); - retval = ERROR_OK; - } /* request target halt if necessary, and schedule further action */ target = targets; @@ -318,23 +314,24 @@ int target_process_reset(struct command_context_s *cmd_ctx, enum target_reset_mo { if (reset_mode!=RESET_RUN) { - if ((jtag_reset_config & RESET_SRST_PULLS_TRST)==0) - target_halt(target); + if ((retval = target_halt(target))!=ERROR_OK) + return retval; } target = target->next; } - if ((retval = jtag_execute_queue()) != ERROR_OK) - { - LOG_WARNING("JTAG communication failed while reset was asserted. Consider using srst_only for reset_config."); - retval = ERROR_OK; - } - target = targets; while (target) { - target->type->deassert_reset(target); - /* We can fail to bring the target into the halted state */ + if ((retval = target->type->deassert_reset(target))!=ERROR_OK) + return retval; + target = target->next; + } + + target = targets; + while (target) + { + /* We can fail to bring the target into the halted state, try after reset has been deasserted */ if (target->reset_halt) { /* wait up to 1 second for halt. */ @@ -342,25 +339,14 @@ int target_process_reset(struct command_context_s *cmd_ctx, enum target_reset_mo if (target->state != TARGET_HALTED) { LOG_WARNING("Failed to reset target into halted mode - issuing halt"); - target->type->halt(target); + if ((retval = target->type->halt(target))!=ERROR_OK) + return retval; } } target = target->next; } - if ((retval = jtag_execute_queue()) != ERROR_OK) - { - LOG_WARNING("JTAG communication failed while deasserting reset."); - retval = ERROR_OK; - } - - if (jtag_reset_config & RESET_SRST_PULLS_TRST) - { - /* If TRST was asserted we need to set up registers again */ - if ((retval = target_examine(cmd_ctx)) != ERROR_OK) - return retval; - } LOG_DEBUG("Waiting for halted stated as appropriate"); @@ -397,7 +383,7 @@ static int default_mmu(struct target_s *target, int *enabled) return ERROR_OK; } -static int default_examine(struct command_context_s *cmd_ctx, struct target_s *target) +static int default_examine(struct target_s *target) { target->type->examined = 1; return ERROR_OK; @@ -415,7 +401,7 @@ int target_examine(struct command_context_s *cmd_ctx) target_t *target = targets; while (target) { - if ((retval = target->type->examine(cmd_ctx, target))!=ERROR_OK) + if ((retval = target->type->examine(target))!=ERROR_OK) return retval; target = target->next; } diff --git a/src/target/target.h b/src/target/target.h index 5d1e5773c..8673ddc03 100644 --- a/src/target/target.h +++ b/src/target/target.h @@ -182,7 +182,7 @@ typedef struct target_type_s * * invoked every time after the jtag chain has been validated/examined */ - int (*examine)(struct command_context_s *cmd_ctx, struct target_s *target); + int (*examine)(struct target_s *target); /* Set up structures for target. * * It is illegal to talk to the target at this stage as this fn is invoked @@ -250,7 +250,7 @@ typedef struct target_timer_callback_s extern int target_register_commands(struct command_context_s *cmd_ctx); extern int target_register_user_commands(struct command_context_s *cmd_ctx); extern int target_init(struct command_context_s *cmd_ctx); -extern int target_examine(struct command_context_s *cmd_ctx); +extern int target_examine(); extern int handle_target(void *priv); extern int target_process_reset(struct command_context_s *cmd_ctx, enum target_reset_mode reset_mode);