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target/arm: opcodes: rename CamelCase symbols and uppercase variables 

No major cross dependencies, mostly changes internal to each
file/function.

Change-Id: I1325560ef0350517d86d4927cb17ceaae81b75d2
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6340
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
Reviewed-by: Xiang W <wxjstz@126.com>
This commit is contained in:
Antonio Borneo 2021-04-28 00:25:03 +02:00
parent c0ea4295df
commit 12d6f6d804
5 changed files with 707 additions and 707 deletions
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766
src/target/arm_disassembler.c
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File diff suppressed because it is too large Load Diff

36
src/target/arm_disassembler.h
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@ -112,11 +112,11 @@ enum arm_instruction_type {
ARM_QDADD, ARM_QDADD,
ARM_QSUB, ARM_QSUB,
ARM_QDSUB, ARM_QDSUB,
ARM_SMLAxy, ARM_SMLAXY,
ARM_SMLALxy, ARM_SMLALXY,
ARM_SMLAWy, ARM_SMLAWY,
ARM_SMULxy, ARM_SMULXY,
ARM_SMULWy, ARM_SMULWY,
ARM_LDRD, ARM_LDRD,
ARM_STRD, ARM_STRD,
@ -133,35 +133,35 @@ union arm_shifter_operand {
uint32_t immediate; uint32_t immediate;
} immediate; } immediate;
struct { struct {
uint8_t Rm; uint8_t rm;
uint8_t shift; /* 0: LSL, 1: LSR, 2: ASR, 3: ROR, 4: RRX */ uint8_t shift; /* 0: LSL, 1: LSR, 2: ASR, 3: ROR, 4: RRX */
uint8_t shift_imm; uint8_t shift_imm;
} immediate_shift; } immediate_shift;
struct { struct {
uint8_t Rm; uint8_t rm;
uint8_t shift; uint8_t shift;
uint8_t Rs; uint8_t rs;
} register_shift; } register_shift;
}; };
struct arm_data_proc_instr { struct arm_data_proc_instr {
int variant; /* 0: immediate, 1: immediate_shift, 2: register_shift */ int variant; /* 0: immediate, 1: immediate_shift, 2: register_shift */
uint8_t S; uint8_t s;
uint8_t Rn; uint8_t rn;
uint8_t Rd; uint8_t rd;
union arm_shifter_operand shifter_operand; union arm_shifter_operand shifter_operand;
}; };
struct arm_load_store_instr { struct arm_load_store_instr {
uint8_t Rd; uint8_t rd;
uint8_t Rn; uint8_t rn;
uint8_t U; uint8_t u;
int index_mode; /* 0: offset, 1: pre-indexed, 2: post-indexed */ int index_mode; /* 0: offset, 1: pre-indexed, 2: post-indexed */
int offset_mode; /* 0: immediate, 1: (scaled) register */ int offset_mode; /* 0: immediate, 1: (scaled) register */
union { union {
uint32_t offset; uint32_t offset;
struct { struct {
uint8_t Rm; uint8_t rm;
uint8_t shift; /* 0: LSL, 1: LSR, 2: ASR, 3: ROR, 4: RRX */ uint8_t shift; /* 0: LSL, 1: LSR, 2: ASR, 3: ROR, 4: RRX */
uint8_t shift_imm; uint8_t shift_imm;
} reg; } reg;
@ -169,11 +169,11 @@ struct arm_load_store_instr {
}; };
struct arm_load_store_multiple_instr { struct arm_load_store_multiple_instr {
uint8_t Rn; uint8_t rn;
uint32_t register_list; uint32_t register_list;
uint8_t addressing_mode; /* 0: IA, 1: IB, 2: DA, 3: DB */ uint8_t addressing_mode; /* 0: IA, 1: IB, 2: DA, 3: DB */
uint8_t S; uint8_t s;
uint8_t W; uint8_t w;
}; };
struct arm_instruction { struct arm_instruction {

310
src/target/arm_opcodes.h
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@ -36,184 +36,184 @@
/* ARM mode instructions */ /* ARM mode instructions */
/* Store multiple increment after /* Store multiple increment after
* Rn: base register * rn: base register
* List: for each bit in list: store register * list: for each bit in list: store register
* S: in privileged mode: store user-mode registers * s: in privileged mode: store user-mode registers
* W = 1: update the base register. W = 0: leave the base register untouched * w = 1: update the base register. w = 0: leave the base register untouched
*/ */
#define ARMV4_5_STMIA(Rn, List, S, W) \ #define ARMV4_5_STMIA(rn, list, s, w) \
(0xe8800000 | ((S) << 22) | ((W) << 21) | ((Rn) << 16) | (List)) (0xe8800000 | ((s) << 22) | ((w) << 21) | ((rn) << 16) | (list))
/* Load multiple increment after /* Load multiple increment after
* Rn: base register * rn: base register
* List: for each bit in list: store register * list: for each bit in list: store register
* S: in privileged mode: store user-mode registers * s: in privileged mode: store user-mode registers
* W = 1: update the base register. W = 0: leave the base register untouched * w = 1: update the base register. w = 0: leave the base register untouched
*/ */
#define ARMV4_5_LDMIA(Rn, List, S, W) \ #define ARMV4_5_LDMIA(rn, list, s, w) \
(0xe8900000 | ((S) << 22) | ((W) << 21) | ((Rn) << 16) | (List)) (0xe8900000 | ((s) << 22) | ((w) << 21) | ((rn) << 16) | (list))
/* MOV r8, r8 */ /* MOV r8, r8 */
#define ARMV4_5_NOP (0xe1a08008) #define ARMV4_5_NOP (0xe1a08008)
/* Move PSR to general purpose register /* Move PSR to general purpose register
* R = 1: SPSR R = 0: CPSR * r = 1: SPSR r = 0: CPSR
* Rn: target register * rn: target register
*/ */
#define ARMV4_5_MRS(Rn, R) (0xe10f0000 | ((R) << 22) | ((Rn) << 12)) #define ARMV4_5_MRS(rn, r) (0xe10f0000 | ((r) << 22) | ((rn) << 12))
/* Store register /* Store register
* Rd: register to store * rd: register to store
* Rn: base register * rn: base register
*/ */
#define ARMV4_5_STR(Rd, Rn) (0xe5800000 | ((Rd) << 12) | ((Rn) << 16)) #define ARMV4_5_STR(rd, rn) (0xe5800000 | ((rd) << 12) | ((rn) << 16))
/* Load register /* Load register
* Rd: register to load * rd: register to load
* Rn: base register * rn: base register
*/ */
#define ARMV4_5_LDR(Rd, Rn) (0xe5900000 | ((Rd) << 12) | ((Rn) << 16)) #define ARMV4_5_LDR(rd, rn) (0xe5900000 | ((rd) << 12) | ((rn) << 16))
/* Move general purpose register to PSR /* Move general purpose register to PSR
* R = 1: SPSR R = 0: CPSR * r = 1: SPSR r = 0: CPSR
* Field: Field mask * field: Field mask
* 1: control field 2: extension field 4: status field 8: flags field * 1: control field 2: extension field 4: status field 8: flags field
* Rm: source register * rm: source register
*/ */
#define ARMV4_5_MSR_GP(Rm, Field, R) \ #define ARMV4_5_MSR_GP(rm, field, r) \
(0xe120f000 | (Rm) | ((Field) << 16) | ((R) << 22)) (0xe120f000 | (rm) | ((field) << 16) | ((r) << 22))
#define ARMV4_5_MSR_IM(Im, Rotate, Field, R) \ #define ARMV4_5_MSR_IM(im, rotate, field, r) \
(0xe320f000 | (Im) | ((Rotate) << 8) | ((Field) << 16) | ((R) << 22)) (0xe320f000 | (im) | ((rotate) << 8) | ((field) << 16) | ((r) << 22))
/* Load Register Word Immediate Post-Index /* Load Register Word Immediate Post-Index
* Rd: register to load * rd: register to load
* Rn: base register * rn: base register
*/ */
#define ARMV4_5_LDRW_IP(Rd, Rn) (0xe4900004 | ((Rd) << 12) | ((Rn) << 16)) #define ARMV4_5_LDRW_IP(rd, rn) (0xe4900004 | ((rd) << 12) | ((rn) << 16))
/* Load Register Halfword Immediate Post-Index /* Load Register Halfword Immediate Post-Index
* Rd: register to load * rd: register to load
* Rn: base register * rn: base register
*/ */
#define ARMV4_5_LDRH_IP(Rd, Rn) (0xe0d000b2 | ((Rd) << 12) | ((Rn) << 16)) #define ARMV4_5_LDRH_IP(rd, rn) (0xe0d000b2 | ((rd) << 12) | ((rn) << 16))
/* Load Register Byte Immediate Post-Index /* Load Register Byte Immediate Post-Index
* Rd: register to load * rd: register to load
* Rn: base register * rn: base register
*/ */
#define ARMV4_5_LDRB_IP(Rd, Rn) (0xe4d00001 | ((Rd) << 12) | ((Rn) << 16)) #define ARMV4_5_LDRB_IP(rd, rn) (0xe4d00001 | ((rd) << 12) | ((rn) << 16))
/* Store register Word Immediate Post-Index /* Store register Word Immediate Post-Index
* Rd: register to store * rd: register to store
* Rn: base register * rn: base register
*/ */
#define ARMV4_5_STRW_IP(Rd, Rn) (0xe4800004 | ((Rd) << 12) | ((Rn) << 16)) #define ARMV4_5_STRW_IP(rd, rn) (0xe4800004 | ((rd) << 12) | ((rn) << 16))
/* Store register Halfword Immediate Post-Index /* Store register Halfword Immediate Post-Index
* Rd: register to store * rd: register to store
* Rn: base register * rn: base register
*/ */
#define ARMV4_5_STRH_IP(Rd, Rn) (0xe0c000b2 | ((Rd) << 12) | ((Rn) << 16)) #define ARMV4_5_STRH_IP(rd, rn) (0xe0c000b2 | ((rd) << 12) | ((rn) << 16))
/* Store register Byte Immediate Post-Index /* Store register Byte Immediate Post-Index
* Rd: register to store * rd: register to store
* Rn: base register * rn: base register
*/ */
#define ARMV4_5_STRB_IP(Rd, Rn) (0xe4c00001 | ((Rd) << 12) | ((Rn) << 16)) #define ARMV4_5_STRB_IP(rd, rn) (0xe4c00001 | ((rd) << 12) | ((rn) << 16))
/* Branch (and Link) /* Branch (and Link)
* Im: Branch target (left-shifted by 2 bits, added to PC) * im: Branch target (left-shifted by 2 bits, added to PC)
* L: 1: branch and link 0: branch only * l: 1: branch and link 0: branch only
*/ */
#define ARMV4_5_B(Im, L) (0xea000000 | (Im) | ((L) << 24)) #define ARMV4_5_B(im, l) (0xea000000 | (im) | ((l) << 24))
/* Branch and exchange (ARM state) /* Branch and exchange (ARM state)
* Rm: register holding branch target address * rm: register holding branch target address
*/ */
#define ARMV4_5_BX(Rm) (0xe12fff10 | (Rm)) #define ARMV4_5_BX(rm) (0xe12fff10 | (rm))
/* Copies two words from two ARM core registers /* Copies two words from two ARM core registers
* into a doubleword extension register, or * into a doubleword extension register, or
* from a doubleword extension register to two ARM core registers. * from a doubleword extension register to two ARM core registers.
* See Armv7-A arch reference manual section A8.8.345 * See Armv7-A arch reference manual section A8.8.345
* Rt: Arm core register 1 * rt: Arm core register 1
* Rt2: Arm core register 2 * rt2: Arm core register 2
* Vm: The doubleword extension register * vm: The doubleword extension register
* M: m = UInt(M:Vm); * m: m = UInt(m:vm);
* op: to_arm_registers = (op == ‘1’); * op: to_arm_registers = (op == ‘1’);
*/ */
#define ARMV4_5_VMOV(op, Rt2, Rt, M, Vm) \ #define ARMV4_5_VMOV(op, rt2, rt, m, vm) \
(0xec400b10 | ((op) << 20) | ((Rt2) << 16) | \ (0xec400b10 | ((op) << 20) | ((rt2) << 16) | \
((Rt) << 12) | ((M) << 5) | (Vm)) ((rt) << 12) | ((m) << 5) | (vm))
/* Moves the value of the FPSCR to an ARM core register /* Moves the value of the FPSCR to an ARM core register
* Rt: Arm core register * rt: Arm core register
*/ */
#define ARMV4_5_VMRS(Rt) (0xeef10a10 | ((Rt) << 12)) #define ARMV4_5_VMRS(rt) (0xeef10a10 | ((rt) << 12))
/* Moves the value of an ARM core register to the FPSCR. /* Moves the value of an ARM core register to the FPSCR.
* Rt: Arm core register * rt: Arm core register
*/ */
#define ARMV4_5_VMSR(Rt) (0xeee10a10 | ((Rt) << 12)) #define ARMV4_5_VMSR(rt) (0xeee10a10 | ((rt) << 12))
/* Store data from coprocessor to consecutive memory /* Store data from coprocessor to consecutive memory
* See Armv7-A arch doc section A8.6.187 * See Armv7-A arch doc section A8.6.187
* P: 1=index mode (offset from Rn) * p: 1=index mode (offset from rn)
* U: 1=add, 0=subtract Rn address with imm * u: 1=add, 0=subtract rn address with imm
* D: Opcode D encoding * d: Opcode D encoding
* W: write back the offset start address to the Rn register * w: write back the offset start address to the rn register
* CP: Coprocessor number (4 bits) * cp: Coprocessor number (4 bits)
* CRd: Coprocessor source register (4 bits) * crd: Coprocessor source register (4 bits)
* Rn: Base register for memory address (4 bits) * rn: Base register for memory address (4 bits)
* imm: Immediate value (0 - 1020, must be divisible by 4) * imm: Immediate value (0 - 1020, must be divisible by 4)
*/ */
#define ARMV4_5_STC(P, U, D, W, CP, CRd, Rn, imm) \ #define ARMV4_5_STC(p, u, d, w, cp, crd, rn, imm) \
(0xec000000 | ((P) << 24) | ((U) << 23) | ((D) << 22) | \ (0xec000000 | ((p) << 24) | ((u) << 23) | ((d) << 22) | \
((W) << 21) | ((Rn) << 16) | ((CRd) << 12) | ((CP) << 8) | ((imm)>>2)) ((w) << 21) | ((rn) << 16) | ((crd) << 12) | ((cp) << 8) | ((imm)>>2))
/* Loads data from consecutive memory to coprocessor /* Loads data from consecutive memory to coprocessor
* See Armv7-A arch doc section A8.6.51 * See Armv7-A arch doc section A8.6.51
* P: 1=index mode (offset from Rn) * p: 1=index mode (offset from rn)
* U: 1=add, 0=subtract Rn address with imm * u: 1=add, 0=subtract rn address with imm
* D: Opcode D encoding * d: Opcode D encoding
* W: write back the offset start address to the Rn register * w: write back the offset start address to the rn register
* CP: Coprocessor number (4 bits) * cp: Coprocessor number (4 bits)
* CRd: Coprocessor dest register (4 bits) * crd: Coprocessor dest register (4 bits)
* Rn: Base register for memory address (4 bits) * rn: Base register for memory address (4 bits)
* imm: Immediate value (0 - 1020, must be divisible by 4) * imm: Immediate value (0 - 1020, must be divisible by 4)
*/ */
#define ARMV4_5_LDC(P, U, D, W, CP, CRd, Rn, imm) \ #define ARMV4_5_LDC(p, u, d, w, cp, crd, rn, imm) \
(0xec100000 | ((P) << 24) | ((U) << 23) | ((D) << 22) | \ (0xec100000 | ((p) << 24) | ((u) << 23) | ((d) << 22) | \
((W) << 21) | ((Rn) << 16) | ((CRd) << 12) | ((CP) << 8) | ((imm) >> 2)) ((w) << 21) | ((rn) << 16) | ((crd) << 12) | ((cp) << 8) | ((imm) >> 2))
/* Move to ARM register from coprocessor /* Move to ARM register from coprocessor
* CP: Coprocessor number * cp: Coprocessor number
* op1: Coprocessor opcode * op1: Coprocessor opcode
* Rd: destination register * rd: destination register
* CRn: first coprocessor operand * crn: first coprocessor operand
* CRm: second coprocessor operand * crm: second coprocessor operand
* op2: Second coprocessor opcode * op2: Second coprocessor opcode
*/ */
#define ARMV4_5_MRC(CP, op1, Rd, CRn, CRm, op2) \ #define ARMV4_5_MRC(cp, op1, rd, crn, crm, op2) \
(0xee100010 | (CRm) | ((op2) << 5) | ((CP) << 8) \ (0xee100010 | (crm) | ((op2) << 5) | ((cp) << 8) \
| ((Rd) << 12) | ((CRn) << 16) | ((op1) << 21)) | ((rd) << 12) | ((crn) << 16) | ((op1) << 21))
/* Move to coprocessor from ARM register /* Move to coprocessor from ARM register
* CP: Coprocessor number * cp: Coprocessor number
* op1: Coprocessor opcode * op1: Coprocessor opcode
* Rd: destination register * rd: destination register
* CRn: first coprocessor operand * crn: first coprocessor operand
* CRm: second coprocessor operand * crm: second coprocessor operand
* op2: Second coprocessor opcode * op2: Second coprocessor opcode
*/ */
#define ARMV4_5_MCR(CP, op1, Rd, CRn, CRm, op2) \ #define ARMV4_5_MCR(cp, op1, rd, crn, crm, op2) \
(0xee000010 | (CRm) | ((op2) << 5) | ((CP) << 8) \ (0xee000010 | (crm) | ((op2) << 5) | ((cp) << 8) \
| ((Rd) << 12) | ((CRn) << 16) | ((op1) << 21)) | ((rd) << 12) | ((crn) << 16) | ((op1) << 21))
/* Breakpoint instruction (ARMv5) /* Breakpoint instruction (ARMv5)
* Im: 16-bit immediate * im: 16-bit immediate
*/ */
#define ARMV5_BKPT(Im) (0xe1200070 | ((Im & 0xfff0) << 4) | (Im & 0xf)) #define ARMV5_BKPT(im) (0xe1200070 | ((im & 0xfff0) << 4) | (im & 0xf))
/* Thumb mode instructions /* Thumb mode instructions
@ -228,45 +228,45 @@
*/ */
/* Store register (Thumb mode) /* Store register (Thumb mode)
* Rd: source register * rd: source register
* Rn: base register * rn: base register
*/ */
#define ARMV4_5_T_STR(Rd, Rn) \ #define ARMV4_5_T_STR(rd, rn) \
((0x6000 | (Rd) | ((Rn) << 3)) | \ ((0x6000 | (rd) | ((rn) << 3)) | \
((0x6000 | (Rd) | ((Rn) << 3)) << 16)) ((0x6000 | (rd) | ((rn) << 3)) << 16))
/* Load register (Thumb state) /* Load register (Thumb state)
* Rd: destination register * rd: destination register
* Rn: base register * rn: base register
*/ */
#define ARMV4_5_T_LDR(Rd, Rn) \ #define ARMV4_5_T_LDR(rd, rn) \
((0x6800 | ((Rn) << 3) | (Rd)) \ ((0x6800 | ((rn) << 3) | (rd)) \
| ((0x6800 | ((Rn) << 3) | (Rd)) << 16)) | ((0x6800 | ((rn) << 3) | (rd)) << 16))
/* Load multiple (Thumb state) /* Load multiple (Thumb state)
* Rn: base register * rn: base register
* List: for each bit in list: store register * list: for each bit in list: store register
*/ */
#define ARMV4_5_T_LDMIA(Rn, List) \ #define ARMV4_5_T_LDMIA(rn, list) \
((0xc800 | ((Rn) << 8) | (List)) \ ((0xc800 | ((rn) << 8) | (list)) \
| ((0xc800 | ((Rn) << 8) | (List)) << 16)) | ((0xc800 | ((rn) << 8) | (list)) << 16))
/* Load register with PC relative addressing /* Load register with PC relative addressing
* Rd: register to load * rd: register to load
*/ */
#define ARMV4_5_T_LDR_PCREL(Rd) \ #define ARMV4_5_T_LDR_PCREL(rd) \
((0x4800 | ((Rd) << 8)) \ ((0x4800 | ((rd) << 8)) \
| ((0x4800 | ((Rd) << 8)) << 16)) | ((0x4800 | ((rd) << 8)) << 16))
/* Move hi register (Thumb mode) /* Move hi register (Thumb mode)
* Rd: destination register * rd: destination register
* Rm: source register * rm: source register
*/ */
#define ARMV4_5_T_MOV(Rd, Rm) \ #define ARMV4_5_T_MOV(rd, rm) \
((0x4600 | ((Rd) & 0x7) | (((Rd) & 0x8) << 4) | \ ((0x4600 | ((rd) & 0x7) | (((rd) & 0x8) << 4) | \
(((Rm) & 0x7) << 3) | (((Rm) & 0x8) << 3)) \ (((rm) & 0x7) << 3) | (((rm) & 0x8) << 3)) \
| ((0x4600 | ((Rd) & 0x7) | (((Rd) & 0x8) << 4) | \ | ((0x4600 | ((rd) & 0x7) | (((rd) & 0x8) << 4) | \
(((Rm) & 0x7) << 3) | (((Rm) & 0x8) << 3)) << 16)) (((rm) & 0x7) << 3) | (((rm) & 0x8) << 3)) << 16))
/* No operation (Thumb mode) /* No operation (Thumb mode)
* NOTE: this is "MOV r8, r8" ... Thumb2 adds two * NOTE: this is "MOV r8, r8" ... Thumb2 adds two
@ -275,63 +275,63 @@
#define ARMV4_5_T_NOP (0x46c0 | (0x46c0 << 16)) #define ARMV4_5_T_NOP (0x46c0 | (0x46c0 << 16))
/* Move immediate to register (Thumb state) /* Move immediate to register (Thumb state)
* Rd: destination register * rd: destination register
* Im: 8-bit immediate value * im: 8-bit immediate value
*/ */
#define ARMV4_5_T_MOV_IM(Rd, Im) \ #define ARMV4_5_T_MOV_IM(rd, im) \
((0x2000 | ((Rd) << 8) | (Im)) \ ((0x2000 | ((rd) << 8) | (im)) \
| ((0x2000 | ((Rd) << 8) | (Im)) << 16)) | ((0x2000 | ((rd) << 8) | (im)) << 16))
/* Branch and Exchange /* Branch and Exchange
* Rm: register containing branch target * rm: register containing branch target
*/ */
#define ARMV4_5_T_BX(Rm) \ #define ARMV4_5_T_BX(rm) \
((0x4700 | ((Rm) << 3)) \ ((0x4700 | ((rm) << 3)) \
| ((0x4700 | ((Rm) << 3)) << 16)) | ((0x4700 | ((rm) << 3)) << 16))
/* Branch (Thumb state) /* Branch (Thumb state)
* Imm: Branch target * imm: Branch target
*/ */
#define ARMV4_5_T_B(Imm) \ #define ARMV4_5_T_B(imm) \
((0xe000 | (Imm)) \ ((0xe000 | (imm)) \
| ((0xe000 | (Imm)) << 16)) | ((0xe000 | (imm)) << 16))
/* Breakpoint instruction (ARMv5) (Thumb state) /* Breakpoint instruction (ARMv5) (Thumb state)
* Im: 8-bit immediate * Im: 8-bit immediate
*/ */
#define ARMV5_T_BKPT(Im) \ #define ARMV5_T_BKPT(im) \
((0xbe00 | (Im)) \ ((0xbe00 | (im)) \
| ((0xbe00 | (Im)) << 16)) | ((0xbe00 | (im)) << 16))
/* Move to Register from Special Register /* Move to Register from Special Register
* 32 bit Thumb2 instruction * 32 bit Thumb2 instruction
* Rd: destination register * rd: destination register
* SYSm: source special register * sysm: source special register
*/ */
#define ARM_T2_MRS(Rd, SYSm) \ #define ARM_T2_MRS(rd, sysm) \
((0xF3EF) | ((0x8000 | (Rd << 8) | SYSm) << 16)) ((0xF3EF) | ((0x8000 | (rd << 8) | sysm) << 16))
/* Move from Register from Special Register /* Move from Register from Special Register
* 32 bit Thumb2 instruction * 32 bit Thumb2 instruction
* Rd: source register * rd: source register
* SYSm: destination special register * sysm: destination special register
*/ */
#define ARM_T2_MSR(SYSm, Rn) \ #define ARM_T2_MSR(sysm, rn) \
((0xF380 | (Rn << 8)) | ((0x8800 | SYSm) << 16)) ((0xF380 | (rn << 8)) | ((0x8800 | sysm) << 16))
/* Change Processor State. /* Change Processor State.
* 16 bit Thumb2 instruction * 16 bit Thumb2 instruction
* Rd: source register * rd: source register
* IF: A_FLAG and/or I_FLAG and/or F_FLAG * IF: A_FLAG and/or I_FLAG and/or F_FLAG
*/ */
#define A_FLAG 4 #define A_FLAG 4
#define I_FLAG 2 #define I_FLAG 2
#define F_FLAG 1 #define F_FLAG 1
#define ARM_T2_CPSID(IF) \ #define ARM_T2_CPSID(_if) \
((0xB660 | (1 << 8) | ((IF)&0x3)) \ ((0xB660 | (1 << 8) | ((_if)&0x3)) \
| ((0xB660 | (1 << 8) | ((IF)&0x3)) << 16)) | ((0xB660 | (1 << 8) | ((_if)&0x3)) << 16))
#define ARM_T2_CPSIE(IF) \ #define ARM_T2_CPSIE(_if) \
((0xB660 | (0 << 8) | ((IF)&0x3)) \ ((0xB660 | (0 << 8) | ((_if)&0x3)) \
| ((0xB660 | (0 << 8) | ((IF)&0x3)) << 16)) | ((0xB660 | (0 << 8) | ((_if)&0x3)) << 16))
#endif /* OPENOCD_TARGET_ARM_OPCODES_H */ #endif /* OPENOCD_TARGET_ARM_OPCODES_H */

186
src/target/arm_simulator.c
View File

@ -31,7 +31,7 @@
#include "register.h" #include "register.h"
#include <helper/log.h> #include <helper/log.h>
static uint32_t arm_shift(uint8_t shift, uint32_t Rm, static uint32_t arm_shift(uint8_t shift, uint32_t rm,
uint32_t shift_amount, uint8_t *carry) uint32_t shift_amount, uint8_t *carry)
{ {
uint32_t return_value = 0; uint32_t return_value = 0;
@ -39,22 +39,22 @@ static uint32_t arm_shift(uint8_t shift, uint32_t Rm,
if (shift == 0x0) { /* LSL */ if (shift == 0x0) { /* LSL */
if ((shift_amount > 0) && (shift_amount <= 32)) { if ((shift_amount > 0) && (shift_amount <= 32)) {
return_value = Rm << shift_amount; return_value = rm << shift_amount;
*carry = Rm >> (32 - shift_amount); *carry = rm >> (32 - shift_amount);
} else if (shift_amount > 32) { } else if (shift_amount > 32) {
return_value = 0x0; return_value = 0x0;
*carry = 0x0; *carry = 0x0;
} else /* (shift_amount == 0) */ } else /* (shift_amount == 0) */
return_value = Rm; return_value = rm;
} else if (shift == 0x1) { /* LSR */ } else if (shift == 0x1) { /* LSR */
if ((shift_amount > 0) && (shift_amount <= 32)) { if ((shift_amount > 0) && (shift_amount <= 32)) {
return_value = Rm >> shift_amount; return_value = rm >> shift_amount;
*carry = (Rm >> (shift_amount - 1)) & 1; *carry = (rm >> (shift_amount - 1)) & 1;
} else if (shift_amount > 32) { } else if (shift_amount > 32) {
return_value = 0x0; return_value = 0x0;
*carry = 0x0; *carry = 0x0;
} else /* (shift_amount == 0) */ } else /* (shift_amount == 0) */
return_value = Rm; return_value = rm;
} else if (shift == 0x2) { /* ASR */ } else if (shift == 0x2) { /* ASR */
if ((shift_amount > 0) && (shift_amount <= 32)) { if ((shift_amount > 0) && (shift_amount <= 32)) {
/* C right shifts of unsigned values are guaranteed to /* C right shifts of unsigned values are guaranteed to
@ -62,11 +62,11 @@ static uint32_t arm_shift(uint8_t shift, uint32_t Rm,
* shift (shift in signed-bit) by adding the sign bit * shift (shift in signed-bit) by adding the sign bit
* manually * manually
*/ */
return_value = Rm >> shift_amount; return_value = rm >> shift_amount;
if (Rm & 0x80000000) if (rm & 0x80000000)
return_value |= 0xffffffff << (32 - shift_amount); return_value |= 0xffffffff << (32 - shift_amount);
} else if (shift_amount > 32) { } else if (shift_amount > 32) {
if (Rm & 0x80000000) { if (rm & 0x80000000) {
return_value = 0xffffffff; return_value = 0xffffffff;
*carry = 0x1; *carry = 0x1;
} else { } else {
@ -74,20 +74,20 @@ static uint32_t arm_shift(uint8_t shift, uint32_t Rm,
*carry = 0x0; *carry = 0x0;
} }
} else /* (shift_amount == 0) */ } else /* (shift_amount == 0) */
return_value = Rm; return_value = rm;
} else if (shift == 0x3) { /* ROR */ } else if (shift == 0x3) { /* ROR */
if (shift_amount == 0) if (shift_amount == 0)
return_value = Rm; return_value = rm;
else { else {
shift_amount = shift_amount % 32; shift_amount = shift_amount % 32;
return_value = (Rm >> shift_amount) | (Rm << (32 - shift_amount)); return_value = (rm >> shift_amount) | (rm << (32 - shift_amount));
*carry = (return_value >> 31) & 0x1; *carry = (return_value >> 31) & 0x1;
} }
} else if (shift == 0x4) { /* RRX */ } else if (shift == 0x4) { /* RRX */
return_value = Rm >> 1; return_value = rm >> 1;
if (*carry) if (*carry)
Rm |= 0x80000000; rm |= 0x80000000;
*carry = Rm & 0x1; *carry = rm & 0x1;
} }
return return_value; return return_value;
@ -111,25 +111,25 @@ static uint32_t arm_shifter_operand(struct arm_sim_interface *sim,
if (variant == 0) /* 32-bit immediate */ if (variant == 0) /* 32-bit immediate */
return_value = shifter_operand.immediate.immediate; return_value = shifter_operand.immediate.immediate;
else if (variant == 1) {/* immediate shift */ else if (variant == 1) {/* immediate shift */
uint32_t Rm = sim->get_reg_mode(sim, shifter_operand.immediate_shift.Rm); uint32_t rm = sim->get_reg_mode(sim, shifter_operand.immediate_shift.rm);
/* adjust RM in case the PC is being read */ /* adjust RM in case the PC is being read */
if (shifter_operand.immediate_shift.Rm == 15) if (shifter_operand.immediate_shift.rm == 15)
Rm += 2 * instruction_size; rm += 2 * instruction_size;
return_value = arm_shift(shifter_operand.immediate_shift.shift, return_value = arm_shift(shifter_operand.immediate_shift.shift,
Rm, shifter_operand.immediate_shift.shift_imm, rm, shifter_operand.immediate_shift.shift_imm,
shifter_carry_out); shifter_carry_out);
} else if (variant == 2) { /* register shift */ } else if (variant == 2) { /* register shift */
uint32_t Rm = sim->get_reg_mode(sim, shifter_operand.register_shift.Rm); uint32_t rm = sim->get_reg_mode(sim, shifter_operand.register_shift.rm);
uint32_t Rs = sim->get_reg_mode(sim, shifter_operand.register_shift.Rs); uint32_t rs = sim->get_reg_mode(sim, shifter_operand.register_shift.rs);
/* adjust RM in case the PC is being read */ /* adjust RM in case the PC is being read */
if (shifter_operand.register_shift.Rm == 15) if (shifter_operand.register_shift.rm == 15)
Rm += 2 * instruction_size; rm += 2 * instruction_size;
return_value = arm_shift(shifter_operand.immediate_shift.shift, return_value = arm_shift(shifter_operand.immediate_shift.shift,
Rm, Rs, shifter_carry_out); rm, rs, shifter_carry_out);
} else { } else {
LOG_ERROR("BUG: shifter_operand.variant not 0, 1 or 2"); LOG_ERROR("BUG: shifter_operand.variant not 0, 1 or 2");
return_value = 0xffffffff; return_value = 0xffffffff;
@ -324,8 +324,8 @@ static int arm_simulate_step_core(struct target *target,
sim->set_reg(sim, 15, target_address); sim->set_reg(sim, 15, target_address);
else if (instruction.type == ARM_BL) { else if (instruction.type == ARM_BL) {
uint32_t old_pc = sim->get_reg(sim, 15); uint32_t old_pc = sim->get_reg(sim, 15);
int T = (sim->get_state(sim) == ARM_STATE_THUMB); int t = (sim->get_state(sim) == ARM_STATE_THUMB);
sim->set_reg_mode(sim, 14, old_pc + 4 + T); sim->set_reg_mode(sim, 14, old_pc + 4 + t);
sim->set_reg(sim, 15, target_address); sim->set_reg(sim, 15, target_address);
} else if (instruction.type == ARM_BX) { } else if (instruction.type == ARM_BX) {
if (target_address & 0x1) if (target_address & 0x1)
@ -335,8 +335,8 @@ static int arm_simulate_step_core(struct target *target,
sim->set_reg(sim, 15, target_address & 0xfffffffe); sim->set_reg(sim, 15, target_address & 0xfffffffe);
} else if (instruction.type == ARM_BLX) { } else if (instruction.type == ARM_BLX) {
uint32_t old_pc = sim->get_reg(sim, 15); uint32_t old_pc = sim->get_reg(sim, 15);
int T = (sim->get_state(sim) == ARM_STATE_THUMB); int t = (sim->get_state(sim) == ARM_STATE_THUMB);
sim->set_reg_mode(sim, 14, old_pc + 4 + T); sim->set_reg_mode(sim, 14, old_pc + 4 + t);
if (target_address & 0x1) if (target_address & 0x1)
sim->set_state(sim, ARM_STATE_THUMB); sim->set_state(sim, ARM_STATE_THUMB);
@ -351,16 +351,16 @@ static int arm_simulate_step_core(struct target *target,
/* data processing instructions, except compare instructions (CMP, CMN, TST, TEQ) */ /* data processing instructions, except compare instructions (CMP, CMN, TST, TEQ) */
else if (((instruction.type >= ARM_AND) && (instruction.type <= ARM_RSC)) else if (((instruction.type >= ARM_AND) && (instruction.type <= ARM_RSC))
|| ((instruction.type >= ARM_ORR) && (instruction.type <= ARM_MVN))) { || ((instruction.type >= ARM_ORR) && (instruction.type <= ARM_MVN))) {
uint32_t Rd, Rn, shifter_operand; uint32_t rd, rn, shifter_operand;
uint8_t C = sim->get_cpsr(sim, 29, 1); uint8_t c = sim->get_cpsr(sim, 29, 1);
uint8_t carry_out; uint8_t carry_out;
Rd = 0x0; rd = 0x0;
/* ARM_MOV and ARM_MVN does not use Rn */ /* ARM_MOV and ARM_MVN does not use Rn */
if ((instruction.type != ARM_MOV) && (instruction.type != ARM_MVN)) if ((instruction.type != ARM_MOV) && (instruction.type != ARM_MVN))
Rn = sim->get_reg_mode(sim, instruction.info.data_proc.Rn); rn = sim->get_reg_mode(sim, instruction.info.data_proc.rn);
else else
Rn = 0; rn = 0;
shifter_operand = arm_shifter_operand(sim, shifter_operand = arm_shifter_operand(sim,
instruction.info.data_proc.variant, instruction.info.data_proc.variant,
@ -368,53 +368,53 @@ static int arm_simulate_step_core(struct target *target,
&carry_out); &carry_out);
/* adjust Rn in case the PC is being read */ /* adjust Rn in case the PC is being read */
if (instruction.info.data_proc.Rn == 15) if (instruction.info.data_proc.rn == 15)
Rn += 2 * instruction_size; rn += 2 * instruction_size;
if (instruction.type == ARM_AND) if (instruction.type == ARM_AND)
Rd = Rn & shifter_operand; rd = rn & shifter_operand;
else if (instruction.type == ARM_EOR) else if (instruction.type == ARM_EOR)
Rd = Rn ^ shifter_operand; rd = rn ^ shifter_operand;
else if (instruction.type == ARM_SUB) else if (instruction.type == ARM_SUB)
Rd = Rn - shifter_operand; rd = rn - shifter_operand;
else if (instruction.type == ARM_RSB) else if (instruction.type == ARM_RSB)
Rd = shifter_operand - Rn; rd = shifter_operand - rn;
else if (instruction.type == ARM_ADD) else if (instruction.type == ARM_ADD)
Rd = Rn + shifter_operand; rd = rn + shifter_operand;
else if (instruction.type == ARM_ADC) else if (instruction.type == ARM_ADC)
Rd = Rn + shifter_operand + (C & 1); rd = rn + shifter_operand + (c & 1);
else if (instruction.type == ARM_SBC) else if (instruction.type == ARM_SBC)
Rd = Rn - shifter_operand - (C & 1) ? 0 : 1; rd = rn - shifter_operand - (c & 1) ? 0 : 1;
else if (instruction.type == ARM_RSC) else if (instruction.type == ARM_RSC)
Rd = shifter_operand - Rn - (C & 1) ? 0 : 1; rd = shifter_operand - rn - (c & 1) ? 0 : 1;
else if (instruction.type == ARM_ORR) else if (instruction.type == ARM_ORR)
Rd = Rn | shifter_operand; rd = rn | shifter_operand;
else if (instruction.type == ARM_BIC) else if (instruction.type == ARM_BIC)
Rd = Rn & ~(shifter_operand); rd = rn & ~(shifter_operand);
else if (instruction.type == ARM_MOV) else if (instruction.type == ARM_MOV)
Rd = shifter_operand; rd = shifter_operand;
else if (instruction.type == ARM_MVN) else if (instruction.type == ARM_MVN)
Rd = ~shifter_operand; rd = ~shifter_operand;
else else
LOG_WARNING("unhandled instruction type"); LOG_WARNING("unhandled instruction type");
if (dry_run_pc) { if (dry_run_pc) {
if (instruction.info.data_proc.Rd == 15) if (instruction.info.data_proc.rd == 15)
*dry_run_pc = Rd & ~1; *dry_run_pc = rd & ~1;
else else
*dry_run_pc = current_pc + instruction_size; *dry_run_pc = current_pc + instruction_size;
return ERROR_OK; return ERROR_OK;
} else { } else {
if (instruction.info.data_proc.Rd == 15) { if (instruction.info.data_proc.rd == 15) {
sim->set_reg_mode(sim, 15, Rd & ~1); sim->set_reg_mode(sim, 15, rd & ~1);
if (Rd & 1) if (rd & 1)
sim->set_state(sim, ARM_STATE_THUMB); sim->set_state(sim, ARM_STATE_THUMB);
else else
sim->set_state(sim, ARM_STATE_ARM); sim->set_state(sim, ARM_STATE_ARM);
return ERROR_OK; return ERROR_OK;
} }
sim->set_reg_mode(sim, instruction.info.data_proc.Rd, Rd); sim->set_reg_mode(sim, instruction.info.data_proc.rd, rd);
LOG_WARNING("no updating of flags yet"); LOG_WARNING("no updating of flags yet");
} }
} }
@ -429,31 +429,31 @@ static int arm_simulate_step_core(struct target *target,
/* load register instructions */ /* load register instructions */
else if ((instruction.type >= ARM_LDR) && (instruction.type <= ARM_LDRSH)) { else if ((instruction.type >= ARM_LDR) && (instruction.type <= ARM_LDRSH)) {
uint32_t load_address = 0, modified_address = 0, load_value = 0; uint32_t load_address = 0, modified_address = 0, load_value = 0;
uint32_t Rn = sim->get_reg_mode(sim, instruction.info.load_store.Rn); uint32_t rn = sim->get_reg_mode(sim, instruction.info.load_store.rn);
/* adjust Rn in case the PC is being read */ /* adjust Rn in case the PC is being read */
if (instruction.info.load_store.Rn == 15) if (instruction.info.load_store.rn == 15)
Rn += 2 * instruction_size; rn += 2 * instruction_size;
if (instruction.info.load_store.offset_mode == 0) { if (instruction.info.load_store.offset_mode == 0) {
if (instruction.info.load_store.U) if (instruction.info.load_store.u)
modified_address = Rn + instruction.info.load_store.offset.offset; modified_address = rn + instruction.info.load_store.offset.offset;
else else
modified_address = Rn - instruction.info.load_store.offset.offset; modified_address = rn - instruction.info.load_store.offset.offset;
} else if (instruction.info.load_store.offset_mode == 1) { } else if (instruction.info.load_store.offset_mode == 1) {
uint32_t offset; uint32_t offset;
uint32_t Rm = sim->get_reg_mode(sim, uint32_t rm = sim->get_reg_mode(sim,
instruction.info.load_store.offset.reg.Rm); instruction.info.load_store.offset.reg.rm);
uint8_t shift = instruction.info.load_store.offset.reg.shift; uint8_t shift = instruction.info.load_store.offset.reg.shift;
uint8_t shift_imm = instruction.info.load_store.offset.reg.shift_imm; uint8_t shift_imm = instruction.info.load_store.offset.reg.shift_imm;
uint8_t carry = sim->get_cpsr(sim, 29, 1); uint8_t carry = sim->get_cpsr(sim, 29, 1);
offset = arm_shift(shift, Rm, shift_imm, &carry); offset = arm_shift(shift, rm, shift_imm, &carry);
if (instruction.info.load_store.U) if (instruction.info.load_store.u)
modified_address = Rn + offset; modified_address = rn + offset;
else else
modified_address = Rn - offset; modified_address = rn - offset;
} else } else
LOG_ERROR("BUG: offset_mode neither 0 (offset) nor 1 (scaled register)"); LOG_ERROR("BUG: offset_mode neither 0 (offset) nor 1 (scaled register)");
@ -463,7 +463,7 @@ static int arm_simulate_step_core(struct target *target,
* the base address register * the base address register
*/ */
load_address = modified_address; load_address = modified_address;
modified_address = Rn; modified_address = rn;
} else if (instruction.info.load_store.index_mode == 1) { } else if (instruction.info.load_store.index_mode == 1) {
/* pre-indexed mode /* pre-indexed mode
* we load from the modified address, and write it * we load from the modified address, and write it
@ -475,17 +475,17 @@ static int arm_simulate_step_core(struct target *target,
* we load from the unmodified address, and write the * we load from the unmodified address, and write the
* modified address back * modified address back
*/ */
load_address = Rn; load_address = rn;
} }
if ((!dry_run_pc) || (instruction.info.load_store.Rd == 15)) { if ((!dry_run_pc) || (instruction.info.load_store.rd == 15)) {
retval = target_read_u32(target, load_address, &load_value); retval = target_read_u32(target, load_address, &load_value);
if (retval != ERROR_OK) if (retval != ERROR_OK)
return retval; return retval;
} }
if (dry_run_pc) { if (dry_run_pc) {
if (instruction.info.load_store.Rd == 15) if (instruction.info.load_store.rd == 15)
*dry_run_pc = load_value & ~1; *dry_run_pc = load_value & ~1;
else else
*dry_run_pc = current_pc + instruction_size; *dry_run_pc = current_pc + instruction_size;
@ -494,10 +494,10 @@ static int arm_simulate_step_core(struct target *target,
if ((instruction.info.load_store.index_mode == 1) || if ((instruction.info.load_store.index_mode == 1) ||
(instruction.info.load_store.index_mode == 2)) (instruction.info.load_store.index_mode == 2))
sim->set_reg_mode(sim, sim->set_reg_mode(sim,
instruction.info.load_store.Rn, instruction.info.load_store.rn,
modified_address); modified_address);
if (instruction.info.load_store.Rd == 15) { if (instruction.info.load_store.rd == 15) {
sim->set_reg_mode(sim, 15, load_value & ~1); sim->set_reg_mode(sim, 15, load_value & ~1);
if (load_value & 1) if (load_value & 1)
sim->set_state(sim, ARM_STATE_THUMB); sim->set_state(sim, ARM_STATE_THUMB);
@ -505,13 +505,13 @@ static int arm_simulate_step_core(struct target *target,
sim->set_state(sim, ARM_STATE_ARM); sim->set_state(sim, ARM_STATE_ARM);
return ERROR_OK; return ERROR_OK;
} }
sim->set_reg_mode(sim, instruction.info.load_store.Rd, load_value); sim->set_reg_mode(sim, instruction.info.load_store.rd, load_value);
} }
} }
/* load multiple instruction */ /* load multiple instruction */
else if (instruction.type == ARM_LDM) { else if (instruction.type == ARM_LDM) {
int i; int i;
uint32_t Rn = sim->get_reg_mode(sim, instruction.info.load_store_multiple.Rn); uint32_t rn = sim->get_reg_mode(sim, instruction.info.load_store_multiple.rn);
uint32_t load_values[16]; uint32_t load_values[16];
int bits_set = 0; int bits_set = 0;
@ -522,24 +522,24 @@ static int arm_simulate_step_core(struct target *target,
switch (instruction.info.load_store_multiple.addressing_mode) { switch (instruction.info.load_store_multiple.addressing_mode) {
case 0: /* Increment after */ case 0: /* Increment after */
/* Rn = Rn; */ /* rn = rn; */
break; break;
case 1: /* Increment before */ case 1: /* Increment before */
Rn = Rn + 4; rn = rn + 4;
break; break;
case 2: /* Decrement after */ case 2: /* Decrement after */
Rn = Rn - (bits_set * 4) + 4; rn = rn - (bits_set * 4) + 4;
break; break;
case 3: /* Decrement before */ case 3: /* Decrement before */
Rn = Rn - (bits_set * 4); rn = rn - (bits_set * 4);
break; break;
} }
for (i = 0; i < 16; i++) { for (i = 0; i < 16; i++) {
if (instruction.info.load_store_multiple.register_list & (1 << i)) { if (instruction.info.load_store_multiple.register_list & (1 << i)) {
if ((!dry_run_pc) || (i == 15)) if ((!dry_run_pc) || (i == 15))
target_read_u32(target, Rn, &load_values[i]); target_read_u32(target, rn, &load_values[i]);
Rn += 4; rn += 4;
} }
} }
@ -551,7 +551,7 @@ static int arm_simulate_step_core(struct target *target,
} else { } else {
int update_cpsr = 0; int update_cpsr = 0;
if (instruction.info.load_store_multiple.S) { if (instruction.info.load_store_multiple.s) {
if (instruction.info.load_store_multiple.register_list & 0x8000) if (instruction.info.load_store_multiple.register_list & 0x8000)
update_cpsr = 1; update_cpsr = 1;
} }
@ -576,8 +576,8 @@ static int arm_simulate_step_core(struct target *target,
} }
/* base register writeback */ /* base register writeback */
if (instruction.info.load_store_multiple.W) if (instruction.info.load_store_multiple.w)
sim->set_reg_mode(sim, instruction.info.load_store_multiple.Rn, Rn); sim->set_reg_mode(sim, instruction.info.load_store_multiple.rn, rn);
if (instruction.info.load_store_multiple.register_list & 0x8000) if (instruction.info.load_store_multiple.register_list & 0x8000)
@ -591,8 +591,8 @@ static int arm_simulate_step_core(struct target *target,
if (dry_run_pc) { if (dry_run_pc) {
/* STM wont affect PC (advance by instruction size */ /* STM wont affect PC (advance by instruction size */
} else { } else {
uint32_t Rn = sim->get_reg_mode(sim, uint32_t rn = sim->get_reg_mode(sim,
instruction.info.load_store_multiple.Rn); instruction.info.load_store_multiple.rn);
int bits_set = 0; int bits_set = 0;
for (i = 0; i < 16; i++) { for (i = 0; i < 16; i++) {
@ -602,30 +602,30 @@ static int arm_simulate_step_core(struct target *target,
switch (instruction.info.load_store_multiple.addressing_mode) { switch (instruction.info.load_store_multiple.addressing_mode) {
case 0: /* Increment after */ case 0: /* Increment after */
/* Rn = Rn; */ /* rn = rn; */
break; break;
case 1: /* Increment before */ case 1: /* Increment before */
Rn = Rn + 4; rn = rn + 4;
break; break;
case 2: /* Decrement after */ case 2: /* Decrement after */
Rn = Rn - (bits_set * 4) + 4; rn = rn - (bits_set * 4) + 4;
break; break;
case 3: /* Decrement before */ case 3: /* Decrement before */
Rn = Rn - (bits_set * 4); rn = rn - (bits_set * 4);
break; break;
} }
for (i = 0; i < 16; i++) { for (i = 0; i < 16; i++) {
if (instruction.info.load_store_multiple.register_list & (1 << i)) { if (instruction.info.load_store_multiple.register_list & (1 << i)) {
target_write_u32(target, Rn, sim->get_reg_mode(sim, i)); target_write_u32(target, rn, sim->get_reg_mode(sim, i));
Rn += 4; rn += 4;
} }
} }
/* base register writeback */ /* base register writeback */
if (instruction.info.load_store_multiple.W) if (instruction.info.load_store_multiple.w)
sim->set_reg_mode(sim, sim->set_reg_mode(sim,
instruction.info.load_store_multiple.Rn, Rn); instruction.info.load_store_multiple.rn, rn);
} }
} else if (!dry_run_pc) { } else if (!dry_run_pc) {

116
src/target/armv8_opcodes.h
View File

@ -26,13 +26,13 @@
#define SYSTEM_CUREL_NONCH 0xF #define SYSTEM_CUREL_NONCH 0xF
#define SYSTEM_AARCH64 0x1 #define SYSTEM_AARCH64 0x1
#define SYSTEM_AAR64_MODE_EL0t 0x0 #define SYSTEM_AAR64_MODE_EL0T 0x0
#define SYSTEM_AAR64_MODE_EL1t 0x4 #define SYSTEM_AAR64_MODE_EL1T 0x4
#define SYSTEM_AAR64_MODE_EL1h 0x5 #define SYSTEM_AAR64_MODE_EL1H 0x5
#define SYSTEM_AAR64_MODE_EL2t 0x8 #define SYSTEM_AAR64_MODE_EL2T 0x8
#define SYSTEM_AAR64_MODE_EL2h 0x9 #define SYSTEM_AAR64_MODE_EL2H 0x9
#define SYSTEM_AAR64_MODE_EL3t 0xC #define SYSTEM_AAR64_MODE_EL3T 0xC
#define SYSTEM_AAR64_MODE_EL3h 0xd #define SYSTEM_AAR64_MODE_EL3H 0xd
#define SYSTEM_DAIF 0b1101101000010001 #define SYSTEM_DAIF 0b1101101000010001
#define SYSTEM_DAIF_MASK 0x3C0 #define SYSTEM_DAIF_MASK 0x3C0
@ -109,26 +109,26 @@
#define SYSTEM_ESR_EL2 0b1110001010010000 #define SYSTEM_ESR_EL2 0b1110001010010000
#define SYSTEM_ESR_EL3 0b1111001010010000 #define SYSTEM_ESR_EL3 0b1111001010010000
#define ARMV8_MRS_DSPSR(Rt) (0xd53b4500 | (Rt)) #define ARMV8_MRS_DSPSR(rt) (0xd53b4500 | (rt))
#define ARMV8_MSR_DSPSR(Rt) (0xd51b4500 | (Rt)) #define ARMV8_MSR_DSPSR(rt) (0xd51b4500 | (rt))
#define ARMV8_MRS_DLR(Rt) (0xd53b4520 | (Rt)) #define ARMV8_MRS_DLR(rt) (0xd53b4520 | (rt))
#define ARMV8_MSR_DLR(Rt) (0xd51b4520 | (Rt)) #define ARMV8_MSR_DLR(rt) (0xd51b4520 | (rt))
/* T32 instruction to access coprocessor registers */ /* T32 instruction to access coprocessor registers */
#define ARMV8_MCR_T1(cp, CRn, opc1, CRm, opc2, Rt) ARMV4_5_MCR(cp, opc1, Rt, CRn, CRm, opc2) #define ARMV8_MCR_T1(cp, crn, opc1, crm, opc2, rt) ARMV4_5_MCR(cp, opc1, rt, crn, crm, opc2)
#define ARMV8_MRC_T1(cp, CRn, opc1, CRm, opc2, Rt) ARMV4_5_MRC(cp, opc1, Rt, CRn, CRm, opc2) #define ARMV8_MRC_T1(cp, crn, opc1, crm, opc2, rt) ARMV4_5_MRC(cp, opc1, rt, crn, crm, opc2)
/* T32 instructions to access DSPSR and DLR */ /* T32 instructions to access DSPSR and DLR */
#define ARMV8_MRC_DSPSR(Rt) ARMV8_MRC_T1(15, 4, 3, 5, 0, Rt) #define ARMV8_MRC_DSPSR(rt) ARMV8_MRC_T1(15, 4, 3, 5, 0, rt)
#define ARMV8_MCR_DSPSR(Rt) ARMV8_MCR_T1(15, 4, 3, 5, 0, Rt) #define ARMV8_MCR_DSPSR(rt) ARMV8_MCR_T1(15, 4, 3, 5, 0, rt)
#define ARMV8_MRC_DLR(Rt) ARMV8_MRC_T1(15, 4, 3, 5, 1, Rt) #define ARMV8_MRC_DLR(rt) ARMV8_MRC_T1(15, 4, 3, 5, 1, rt)
#define ARMV8_MCR_DLR(Rt) ARMV8_MCR_T1(15, 4, 3, 5, 1, Rt) #define ARMV8_MCR_DLR(rt) ARMV8_MCR_T1(15, 4, 3, 5, 1, rt)
#define ARMV8_DCPS1(IM) (0xd4a00001 | (((IM) & 0xFFFF) << 5)) #define ARMV8_DCPS1(im) (0xd4a00001 | (((im) & 0xFFFF) << 5))
#define ARMV8_DCPS2(IM) (0xd4a00002 | (((IM) & 0xFFFF) << 5)) #define ARMV8_DCPS2(im) (0xd4a00002 | (((im) & 0xFFFF) << 5))
#define ARMV8_DCPS3(IM) (0xd4a00003 | (((IM) & 0xFFFF) << 5)) #define ARMV8_DCPS3(im) (0xd4a00003 | (((im) & 0xFFFF) << 5))
#define ARMV8_DCPS(EL, IM) (0xd4a00000 | (((IM) & 0xFFFF) << 5) | EL) #define ARMV8_DCPS(el, im) (0xd4a00000 | (((im) & 0xFFFF) << 5) | el)
#define ARMV8_DCPS_T1(EL) (0xf78f8000 | EL) #define ARMV8_DCPS_T1(el) (0xf78f8000 | el)
#define ARMV8_DRPS 0xd6bf03e0 #define ARMV8_DRPS 0xd6bf03e0
#define ARMV8_ERET_T1 0xf3de8f00 #define ARMV8_ERET_T1 0xf3de8f00
@ -137,54 +137,54 @@
#define ARMV8_ISB 0xd5033fdf #define ARMV8_ISB 0xd5033fdf
#define ARMV8_ISB_SY_T1 0xf3bf8f6f #define ARMV8_ISB_SY_T1 0xf3bf8f6f
#define ARMV8_MRS(System, Rt) (0xd5300000 | ((System) << 5) | (Rt)) #define ARMV8_MRS(system, rt) (0xd5300000 | ((system) << 5) | (rt))
/* ARM V8 Move to system register. */ /* ARM V8 Move to system register. */
#define ARMV8_MSR_GP(System, Rt) \ #define ARMV8_MSR_GP(system, rt) \
(0xd5100000 | ((System) << 5) | (Rt)) (0xd5100000 | ((system) << 5) | (rt))
/* ARM V8 Move immediate to process state field. */ /* ARM V8 Move immediate to process state field. */
#define ARMV8_MSR_IM(Op1, CRm, Op2) \ #define ARMV8_MSR_IM(op1, crm, op2) \
(0xd500401f | ((Op1) << 16) | ((CRm) << 8) | ((Op2) << 5)) (0xd500401f | ((op1) << 16) | ((crm) << 8) | ((op2) << 5))
#define ARMV8_MRS_T1(R, M1, Rd, M) (0xF3E08020 | (R << 20) | (M1 << 16) | (Rd << 8) | (M << 4)) #define ARMV8_MRS_T1(r, m1, rd, m) (0xF3E08020 | (r << 20) | (m1 << 16) | (rd << 8) | (m << 4))
#define ARMV8_MRS_xPSR_T1(R, Rd) (0xF3EF8000 | (R << 20) | (Rd << 8)) #define ARMV8_MRS_xPSR_T1(r, rd) (0xF3EF8000 | (r << 20) | (rd << 8))
#define ARMV8_MSR_GP_T1(R, M1, Rd, M) (0xF3808020 | (R << 20) | (M1 << 8) | (Rd << 16) | (M << 4)) #define ARMV8_MSR_GP_T1(r, m1, rd, m) (0xF3808020 | (r << 20) | (m1 << 8) | (rd << 16) | (m << 4))
#define ARMV8_MSR_GP_xPSR_T1(R, Rn, mask) (0xF3808000 | (R << 20) | (Rn << 16) | (mask << 8)) #define ARMV8_MSR_GP_xPSR_T1(r, rn, mask) (0xF3808000 | (r << 20) | (rn << 16) | (mask << 8))
#define ARMV8_BKPT(Im) (0xD4200000 | ((Im & 0xffff) << 5)) #define ARMV8_BKPT(im) (0xD4200000 | ((im & 0xffff) << 5))
#define ARMV8_HLT(Im) (0x0D4400000 | ((Im & 0xffff) << 5)) #define ARMV8_HLT(im) (0x0D4400000 | ((im & 0xffff) << 5))
#define ARMV8_HLT_A1(Im) (0xE1000070 | ((Im & 0xFFF0) << 4) | (Im & 0xF)) #define ARMV8_HLT_A1(im) (0xE1000070 | ((im & 0xFFF0) << 4) | (im & 0xF))
#define ARMV8_HLT_T1(Im) (0xba80 | (Im & 0x3f)) #define ARMV8_HLT_T1(im) (0xba80 | (im & 0x3f))
#define ARMV8_MOVFSP_64(Rt) ((1 << 31) | 0x11000000 | (0x1f << 5) | (Rt)) #define ARMV8_MOVFSP_64(rt) ((1 << 31) | 0x11000000 | (0x1f << 5) | (rt))
#define ARMV8_MOVTSP_64(Rt) ((1 << 31) | 0x11000000 | (Rt << 5) | (0x1F)) #define ARMV8_MOVTSP_64(rt) ((1 << 31) | 0x11000000 | (rt << 5) | (0x1F))
#define ARMV8_MOVFSP_32(Rt) (0x11000000 | (0x1f << 5) | (Rt)) #define ARMV8_MOVFSP_32(rt) (0x11000000 | (0x1f << 5) | (rt))
#define ARMV8_MOVTSP_32(Rt) (0x11000000 | (Rt << 5) | (0x1F)) #define ARMV8_MOVTSP_32(rt) (0x11000000 | (rt << 5) | (0x1F))
#define ARMV8_LDRB_IP(Rd, Rn) (0x38401400 | (Rn << 5) | Rd) #define ARMV8_LDRB_IP(rd, rn) (0x38401400 | (rn << 5) | rd)
#define ARMV8_LDRH_IP(Rd, Rn) (0x78402400 | (Rn << 5) | Rd) #define ARMV8_LDRH_IP(rd, rn) (0x78402400 | (rn << 5) | rd)
#define ARMV8_LDRW_IP(Rd, Rn) (0xb8404400 | (Rn << 5) | Rd) #define ARMV8_LDRW_IP(rd, rn) (0xb8404400 | (rn << 5) | rd)
#define ARMV8_LDRB_IP_T3(Rd, Rn) (0xf8100b01 | (Rn << 16) | (Rd << 12)) #define ARMV8_LDRB_IP_T3(rd, rn) (0xf8100b01 | (rn << 16) | (rd << 12))
#define ARMV8_LDRH_IP_T3(Rd, Rn) (0xf8300b02 | (Rn << 16) | (Rd << 12)) #define ARMV8_LDRH_IP_T3(rd, rn) (0xf8300b02 | (rn << 16) | (rd << 12))
#define ARMV8_LDRW_IP_T3(Rd, Rn) (0xf8500b04 | (Rn << 16) | (Rd << 12)) #define ARMV8_LDRW_IP_T3(rd, rn) (0xf8500b04 | (rn << 16) | (rd << 12))
#define ARMV8_STRB_IP(Rd, Rn) (0x38001400 | (Rn << 5) | Rd) #define ARMV8_STRB_IP(rd, rn) (0x38001400 | (rn << 5) | rd)
#define ARMV8_STRH_IP(Rd, Rn) (0x78002400 | (Rn << 5) | Rd) #define ARMV8_STRH_IP(rd, rn) (0x78002400 | (rn << 5) | rd)
#define ARMV8_STRW_IP(Rd, Rn) (0xb8004400 | (Rn << 5) | Rd) #define ARMV8_STRW_IP(rd, rn) (0xb8004400 | (rn << 5) | rd)
#define ARMV8_STRB_IP_T3(Rd, Rn) (0xf8000b01 | (Rn << 16) | (Rd << 12)) #define ARMV8_STRB_IP_T3(rd, rn) (0xf8000b01 | (rn << 16) | (rd << 12))
#define ARMV8_STRH_IP_T3(Rd, Rn) (0xf8200b02 | (Rn << 16) | (Rd << 12)) #define ARMV8_STRH_IP_T3(rd, rn) (0xf8200b02 | (rn << 16) | (rd << 12))
#define ARMV8_STRW_IP_T3(Rd, Rn) (0xf8400b04 | (Rn << 16) | (Rd << 12)) #define ARMV8_STRW_IP_T3(rd, rn) (0xf8400b04 | (rn << 16) | (rd << 12))
#define ARMV8_MOV_GPR_VFP(Rd, Rn, Index) (0x4e083c00 | (Index << 20) | (Rn << 5) | Rd) #define ARMV8_MOV_GPR_VFP(rd, rn, index) (0x4e083c00 | (index << 20) | (rn << 5) | rd)
#define ARMV8_MOV_VFP_GPR(Rd, Rn, Index) (0x4e081c00 | (Index << 20) | (Rn << 5) | Rd) #define ARMV8_MOV_VFP_GPR(rd, rn, index) (0x4e081c00 | (index << 20) | (rn << 5) | rd)
#define ARMV8_MRS_FPCR(Rt) (0xd53b4400 | (Rt)) #define ARMV8_MRS_FPCR(rt) (0xd53b4400 | (rt))
#define ARMV8_MRS_FPSR(Rt) (0xd53b4420 | (Rt)) #define ARMV8_MRS_FPSR(rt) (0xd53b4420 | (rt))
#define ARMV8_MSR_FPCR(Rt) (0xd51b4400 | (Rt)) #define ARMV8_MSR_FPCR(rt) (0xd51b4400 | (rt))
#define ARMV8_MSR_FPSR(Rt) (0xd51b4420 | (Rt)) #define ARMV8_MSR_FPSR(rt) (0xd51b4420 | (rt))
#define ARMV8_SYS(System, Rt) (0xD5080000 | ((System) << 5) | Rt) #define ARMV8_SYS(system, rt) (0xD5080000 | ((system) << 5) | rt)
enum armv8_opcode { enum armv8_opcode {
READ_REG_CTR, READ_REG_CTR,