interesting
/
riscv-openocd
mirror of https://github.com/riscv/riscv-openocd.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
riscv-openocd/tcl/target/kl25z_hla.cfg

64 lines
1.7 KiB
INI
Raw Normal View History

target: add kl25z HLA (stlink) config Based on Nemuisan Tokusei's. Untested, but original config was reported to work ok. Change-Id: Ic991dce55bfca266880081fe2bbd9e6e263b0fc0 Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/1803 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2013-11-07 13:26:45 -06:00
# MKL25Z128VLK4
# FreeScale Cortex-M0plus with 128kB Flash and 16kB Local On-Chip SRAM
if { [info exists CHIPNAME] == 0 } {
set _CHIPNAME kl25z
}
if { [info exists CPUTAPID] == 0 } {
set _CPUTAPID 0x0BC11477
}
if { [info exists WORKAREASIZE] == 0 } {
set _WORKAREASIZE 0x3000
}
if { [info exists TRANSPORT] == 0 } {
set _TRANSPORT hla_swd
}
transport select $_TRANSPORT
hla newtap $_CHIPNAME cpu -expected-id $_CPUTAPID
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME hla_target -chain-position $_TARGETNAME
kinetis: Revise CPU un-securing code Old version of the code had several problems, among them are: * Located in a generic ADI source file instead of some Kinetis specific location * Incorrect MCU detection code that would read generic ARM ID registers * Presence of SRST line was mandatory * There didn't seem to be any place where after SRST line assertion it would be de-asserted. * Reset was asserted after waiting for "Flash Controller Ready" bit to be set, which contradicts official programming guide AN4835 * Mass erase algorithm implemented by that code was very strange: ** After mass erase was initiated instead of just polling for the state of "Mass Erase Acknowledged" bit the code would repeatedly initiate mass erase AND poll the state of the "Mass Erase Acknowledged" ** Instead of just polling for the state of "Flash Mass Erase in Progress"(bit 0 in Control register) to wait for the end of the mass erase operation the code would: write 0 to Control register, read out Status register ignoring the result and then read Control register again and see if it is zero. * dap_syssec_kinetis_mdmap assumed that previously selected(before it was called) AP was 0. This commit moves all of the code to kinetis flash driver and introduces three new commands: o "kinetis mdm check_security" -- the intent of that function is to be used as 'examine-end' hook for any Kinetis target that has that kind of JTAG/SWD security mechanism. o "kinetis mdm mass_erase"" -- This function removes secure status from MCU be performing special version of flash mass erase. o "kinetis mdm test_securing" -- Function that allows to test securing fucntionality. All it does is erase the page with flash security settings thus making MCU 'secured'. New version of the code implements the algorithms specified in AN4835 "Production Flash Programming Best Practices for Kinetis K- and L-series MCUs", specifically sections 4.1.1 and 4.2.1. It also adds KL26 MCU to the list of devices for which this security check is performed. Implementing that algorithm also allowed to simplify mass command in kinetis driver, since we no longer need to write security bytes. The result that the old version of mass erase code can now be acheived using 'kinetis mdm mass_erase' Tested on accidentally locked FRDM-KL26Z with KL26 Kinetis MCU. Change-Id: Ic085195edfd963dda9d3d4d8acd1e40cc366b16b Signed-off-by: Andrey Smrinov <andrew.smirnov@gmail.com> Reviewed-on: http://openocd.zylin.com/2034 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com> Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2014-03-08 16:42:28 -06:00
# It is important that "kinetis mdm check_security" is called for
# 'examine-end' event and not 'eximine-start'. Calling it in 'examine-start'
# causes "kinetis mdm check_security" to fail the first time openocd
# calls it when it tries to connect after the CPU has been power-cycled.
$_CHIPNAME.cpu configure -event examine-end {
kinetis mdm check_security
}
target: add kl25z HLA (stlink) config Based on Nemuisan Tokusei's. Untested, but original config was reported to work ok. Change-Id: Ic991dce55bfca266880081fe2bbd9e6e263b0fc0 Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/1803 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2013-11-07 13:26:45 -06:00
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
flash bank pflash kinetis 0x00000000 0x20000 0 4 $_TARGETNAME
proc kl25z_enable_pll {} {
echo "KL25Z: Enabling PLL"
# SIM->CLKDIV1 = (uint32_t)0x00020000UL; /* Update system prescalers */
mww 0x40048044 0x00020000
# /* Switch to FEI Mode */
# MCG->C1 = (uint8_t)0x06U;
mwb 0x40064000 0x06
# MCG->C2 = (uint8_t)0x00U;
mwb 0x40064001 0x00
# /* MCG->C4: DMX32=0,DRST_DRS=1 */
# MCG->C4 = (uint8_t)((MCG->C4 & (uint8_t)~(uint8_t)0xC0U) | (uint8_t)0x20U);
mwb 0x40064003 0x37
#OSC0->CR = (uint8_t)0x80U;
mwb 0x40065000 0x80
# MCG->C5 = (uint8_t)0x00U;
mwb 0x40064004 0x00
# MCG->C6 = (uint8_t)0x00U;
mwb 0x40064005 0x00
sleep 100
}
$_TARGETNAME configure -event reset-init {
kl25z_enable_pll
}