riscv-openocd/tcl/target/stm32f3x.cfg

# script for stm32f3x family

#
# stm32 devices support both JTAG and SWD transports.
#
source [find target/swj-dp.tcl]
source [find mem_helper.tcl]

if { [info exists CHIPNAME] } {
   set _CHIPNAME $CHIPNAME
} else {
   set _CHIPNAME stm32f3x
}

set _ENDIAN little

# Work-area is a space in RAM used for flash programming
# By default use 16kB
if { [info exists WORKAREASIZE] } {
   set _WORKAREASIZE $WORKAREASIZE
} else {
   set _WORKAREASIZE 0x4000
}

# JTAG speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz
#
# Since we may be running of an RC oscilator, we crank down the speed a
# bit more to be on the safe side. Perhaps superstition, but if are
# running off a crystal, we can run closer to the limit. Note
# that there can be a pretty wide band where things are more or less stable.
adapter_khz 1000

adapter_nsrst_delay 100
if {[using_jtag]} {
 jtag_ntrst_delay 100
}

#jtag scan chain
if { [info exists CPUTAPID] } {
   set _CPUTAPID $CPUTAPID
} else {
   if { [using_jtag] } {
      # See STM Document RM0316
      # Section 29.6.3 - corresponds to Cortex-M4 r0p1
      set _CPUTAPID 0x4ba00477
   } {
      set _CPUTAPID 0x2ba01477
   }
}

swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID

if { [info exists BSTAPID] } {
   set _BSTAPID $BSTAPID
} else {
  # STM Document RM0316 rev 5 for STM32F302/303 B/C size
  set _BSTAPID1 0x06422041
  # STM Document RM0313 rev 3 for STM32F37x
  set _BSTAPID2 0x06432041
  #  STM Document RM364 rev 1 for STM32F334
  set _BSTAPID3 0x06438041
  #  STM Document RM316 rev 5 for STM32F303 6/8 size
  #  STM Document RM365 rev 3 for STM32F302 6/8 size
  #  STM Document RM366 rev 2 for STM32F301 6/8 size
  set _BSTAPID4 0x06439041
  #  STM Document RM016 rev 5 for STM32F303 D/E size
  set _BSTAPID5 0x06446041
}

if {[using_jtag]} {
 swj_newdap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID1 \
 -expected-id $_BSTAPID2 -expected-id $_BSTAPID3 \
 -expected-id $_BSTAPID4 -expected-id $_BSTAPID5
}

set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME

$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0

set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME stm32f1x 0 0 0 0 $_TARGETNAME

reset_config srst_nogate

if {![using_hla]} {
   # if srst is not fitted use SYSRESETREQ to
   # perform a soft reset
   cortex_m reset_config sysresetreq
}

proc stm32f3x_default_reset_start {} {
	# Reset clock is HSI (8 MHz)
	adapter_khz 1000
}

proc stm32f3x_default_examine_end {} {
	# Enable debug during low power modes (uses more power)
	mmw 0xe0042004 0x00000007 0 ;# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP

	# Stop watchdog counters during halt
	mmw 0xe0042008 0x00001800 0 ;# DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
}

proc stm32f3x_default_reset_init {} {
	# Configure PLL to boost clock to HSI x 8 (64 MHz)
	mww 0x40021004 0x00380400   ;# RCC_CFGR = PLLMUL[3:1] | PPRE1[2]
	mmw 0x40021000 0x01000000 0 ;# RCC_CR |= PLLON
	mww 0x40022000 0x00000012   ;# FLASH_ACR = PRFTBE | LATENCY[1]
	sleep 10                    ;# Wait for PLL to lock
	mmw 0x40021004 0x00000002 0 ;# RCC_CFGR |= SW[1]

	# Boost JTAG frequency
	adapter_khz 8000
}

# Default hooks
$_TARGETNAME configure -event examine-end { stm32f3x_default_examine_end }
$_TARGETNAME configure -event reset-start { stm32f3x_default_reset_start }
$_TARGETNAME configure -event reset-init { stm32f3x_default_reset_init }

$_TARGETNAME configure -event trace-config {
	# Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
	# change this value accordingly to configure trace pins
	# assignment
	mmw 0xe0042004 0x00000020 0
}