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riscv-openocd/tcl/board/avnet_ultrazed-eg.cfg

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tcl/board: add SPDX tag For historical reasons, no license information was added to the tcl files. This makes trivial adding the SPDX tag through script: fgrep -rL SPDX tcl/board | while read a;do \ sed -i '1{i# SPDX-License-Identifier: GPL-2.0-or-later\n }' $a;done With no specific license information from the author, let's extend the OpenOCD project license GPL-2.0-or-later to the files. Change-Id: Ibcf7da62e842aafd036a78db9ea2b9f11f79af16 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/7028 Tested-by: jenkins Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
2022-06-12 16:48:05 -05:00
# SPDX-License-Identifier: GPL-2.0-or-later
tcl/board: add configuration for the avnet ultrazed-eg starter kit also contains target configuration for the Xilinx UltraScale+ platform Change-Id: I6300cbc85c1ed71df71d8aaca59500bbf18f0093 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com> Reviewed-on: http://openocd.zylin.com/4467 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-03-13 11:03:38 -05:00
#
# AVNET UltraZED EG StarterKit
Correct ZynqMP configuration to be appropriately named The xilinx_ultrascale.cfg target is actually the configuration for a ZynqMP, which is a combination of an UltraScale+ FPGA core and a quad core A53. Update the filename/comments to reflect this, and include the tap IDs for all known FPGA cores for this part. Change-Id: I70dfcc99861a482b83b6a795e83021d9cf1fe047 Signed-off-by: Jonathan McDowell <noodles@earth.li> Reviewed-on: http://openocd.zylin.com/4850 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2019-01-14 04:51:37 -06:00
# ZynqMP UlraScale-EG plus IO Carrier with on-board digilent smt2
tcl/board: add configuration for the avnet ultrazed-eg starter kit also contains target configuration for the Xilinx UltraScale+ platform Change-Id: I6300cbc85c1ed71df71d8aaca59500bbf18f0093 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com> Reviewed-on: http://openocd.zylin.com/4467 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-03-13 11:03:38 -05:00
#
source [find interface/ftdi/digilent_jtag_smt2_nc.cfg]
# jtag transport only
transport select jtag
# reset lines are not wired
reset_config none
# slow default clock
tcl: replace the deprecated commands with "adapter ..." Avoid annoying "deprecated" messages while running the scripts distributed with OpenOCD code. Change automatically created with commands sed -i 's/adapter_khz/adapter speed/g' $(find tcl/ -type f) sed -i 's/adapter_nsrst_delay/adapter srst delay/g' $(find tcl/ -type f) sed -i 's/adapter_nsrst_assert_width/adapter srst pulse_width/g' $(find tcl/ -type f) Minor indentation issue fixed manually in tcl/board/at91sam9g20-ek.cfg tcl/target/at91sam9260_ext_RAM_ext_flash.cfg Change-Id: I425fd56c0c88cd6b06124621306eeb89166dfe71 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5284 Tested-by: jenkins Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
2019-08-23 08:51:00 -05:00
adapter speed 1000
tcl/board: add configuration for the avnet ultrazed-eg starter kit also contains target configuration for the Xilinx UltraScale+ platform Change-Id: I6300cbc85c1ed71df71d8aaca59500bbf18f0093 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com> Reviewed-on: http://openocd.zylin.com/4467 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-03-13 11:03:38 -05:00
set CHIPNAME uscale
Correct ZynqMP configuration to be appropriately named The xilinx_ultrascale.cfg target is actually the configuration for a ZynqMP, which is a combination of an UltraScale+ FPGA core and a quad core A53. Update the filename/comments to reflect this, and include the tap IDs for all known FPGA cores for this part. Change-Id: I70dfcc99861a482b83b6a795e83021d9cf1fe047 Signed-off-by: Jonathan McDowell <noodles@earth.li> Reviewed-on: http://openocd.zylin.com/4850 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2019-01-14 04:51:37 -06:00
source [find target/xilinx_zynqmp.cfg]