90 lines
3.1 KiB
INI
90 lines
3.1 KiB
INI
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#
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# NXP i.MX8QuadMax
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#
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME imx8qm
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}
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# CoreSight Debug Access Port (DAP)
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if { [info exists DAP_TAPID] } {
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set _DAP_TAPID $DAP_TAPID
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} else {
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# TAPID is from FreeScale!
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set _DAP_TAPID 0x1890101d
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}
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jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x01 -irmask 0x0f \
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-expected-id $_DAP_TAPID
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dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
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# AXI: Main SOC bus on AP #0
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target create ${_CHIPNAME}.axi mem_ap -dap ${_CHIPNAME}.dap -ap-num 0
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# 4x Cortex-A53 on AP #6
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set _A53_DBGBASE {0x80410000 0x80510000 0x80610000 0x80710000}
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set _A53_CTIBASE {0x80420000 0x80520000 0x80620000 0x80720000}
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cti create $_CHIPNAME.a53_cti.0 -dap $_CHIPNAME.dap \
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-ap-num 6 -baseaddr [lindex $_A53_CTIBASE 0]
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cti create $_CHIPNAME.a53_cti.1 -dap $_CHIPNAME.dap \
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-ap-num 6 -baseaddr [lindex $_A53_CTIBASE 1]
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cti create $_CHIPNAME.a53_cti.2 -dap $_CHIPNAME.dap \
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-ap-num 6 -baseaddr [lindex $_A53_CTIBASE 2]
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cti create $_CHIPNAME.a53_cti.3 -dap $_CHIPNAME.dap \
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-ap-num 6 -baseaddr [lindex $_A53_CTIBASE 3]
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target create $_CHIPNAME.a53.0 aarch64 -dap $_CHIPNAME.dap \
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-cti $_CHIPNAME.a53_cti.0 -dbgbase [lindex $_A53_DBGBASE 0]
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target create $_CHIPNAME.a53.1 aarch64 -dap $_CHIPNAME.dap \
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-cti $_CHIPNAME.a53_cti.1 -dbgbase [lindex $_A53_DBGBASE 1] -defer-examine
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target create $_CHIPNAME.a53.2 aarch64 -dap $_CHIPNAME.dap \
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-cti $_CHIPNAME.a53_cti.2 -dbgbase [lindex $_A53_DBGBASE 2] -defer-examine
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target create $_CHIPNAME.a53.3 aarch64 -dap $_CHIPNAME.dap \
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-cti $_CHIPNAME.a53_cti.3 -dbgbase [lindex $_A53_DBGBASE 3] -defer-examine
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# 2x Cortex-A72 on AP #6
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set _A72_DBGBASE {0x80210000 0x80310000}
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set _A72_CTIBASE {0x80220000 0x80220000}
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cti create $_CHIPNAME.a72_cti.0 -dap $_CHIPNAME.dap \
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-ap-num 6 -baseaddr [lindex $_A72_CTIBASE 0]
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cti create $_CHIPNAME.a72_cti.1 -dap $_CHIPNAME.dap \
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-ap-num 6 -baseaddr [lindex $_A72_CTIBASE 1]
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target create $_CHIPNAME.a72.0 aarch64 -dap $_CHIPNAME.dap \
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-cti $_CHIPNAME.a72_cti.0 -dbgbase [lindex $_A72_DBGBASE 0] -defer-examine
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target create $_CHIPNAME.a72.1 aarch64 -dap $_CHIPNAME.dap \
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-cti $_CHIPNAME.a72_cti.1 -dbgbase [lindex $_A72_DBGBASE 1] -defer-examine
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# All Cortex-A in SMP
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target smp \
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$_CHIPNAME.a53.0 \
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$_CHIPNAME.a53.1 \
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$_CHIPNAME.a53.2 \
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$_CHIPNAME.a53.3 \
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$_CHIPNAME.a72.0 \
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$_CHIPNAME.a72.1
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# SCU: Cortex-M4 core
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# always running imx SC firmware
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target create ${_CHIPNAME}.scu cortex_m -dap ${_CHIPNAME}.dap -ap-num 1
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# AHB from SCU perspective
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target create ${_CHIPNAME}.scu_ahb mem_ap -dap ${_CHIPNAME}.dap -ap-num 4
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# Cortex-M4 M4_0 core on AP #2 (default off)
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target create ${_CHIPNAME}.m4_0 cortex_m -dap ${_CHIPNAME}.dap -ap-num 2 \
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-defer-examine
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# Cortex-M4 M4_1 core on AP #3 (default off)
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target create ${_CHIPNAME}.m4_1 cortex_m -dap ${_CHIPNAME}.dap -ap-num 3 \
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-defer-examine
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# Debug APB bus
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target create ${_CHIPNAME}.apb mem_ap -dap ${_CHIPNAME}.dap -ap-num 6
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# Default target is boot core a53.0
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targets $_CHIPNAME.a53.0
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