riscv-openocd/tcl/target/esp32s2.cfg

# SPDX-License-Identifier: GPL-2.0-or-later
#

# Source the ESP common configuration file.
source [find target/esp_common.cfg]

# Target specific global variables
set _CHIPNAME 					"esp32s2"
set _CPUTAPID 					0x120034e5
set _ESP_ARCH					"xtensa"
set _ONLYCPU					1
set _ESP_SMP_TARGET				0
set _ESP_SMP_BREAK 				1
set _ESP_EFUSE_MAC_ADDR_REG  	0x3f41A004

proc esp32s2_memprot_is_enabled { } {
	# IRAM0, DPORT_PMS_PRO_IRAM0_0_REG
	if { [get_mmr_bit 0x3f4c1010 0] != 0 } {
		return 1
	}
	# DRAM0, DPORT_PMS_PRO_DRAM0_0_REG
	if { [get_mmr_bit 0x3f4c1028 0] != 0 } {
		return 1
	}
	# PERI1, DPORT_PMS_PRO_DPORT_0_REG
	if { [get_mmr_bit 0x3f4c103c 0] != 0 } {
		return 1
	}
	# PERI2, DPORT_PMS_PRO_AHB_0_REG
	if { [get_mmr_bit 0x3f4c105c 0] != 0 } {
		return 1
	}
	return 0
}

proc esp32s2_soc_reset { } {
	soft_reset_halt
}

create_esp_target $_ESP_ARCH

source [find target/xtensa-core-esp32s2.cfg]