riscv-openocd/tcl/target/esp32s2.cfg

# SPDX-License-Identifier: GPL-2.0-or-later
#
# The ESP32-S2 only supports JTAG.
transport select jtag

set CPU_MAX_ADDRESS 0xFFFFFFFF
source [find bitsbytes.tcl]
source [find memory.tcl]
source [find mmr_helpers.tcl]
# Source the ESP common configuration file
source [find target/esp_common.cfg]

if { [info exists CHIPNAME] } {
	set _CHIPNAME $CHIPNAME
} else {
	set _CHIPNAME esp32s2
}

if { [info exists CPUTAPID] } {
	set _CPUTAPID $CPUTAPID
} else {
	set _CPUTAPID 0x120034e5
}

set _TARGETNAME $_CHIPNAME
set _CPUNAME cpu
set _TAPNAME $_CHIPNAME.$_CPUNAME

jtag newtap $_CHIPNAME $_CPUNAME -irlen 5 -expected-id $_CPUTAPID

proc esp32s2_memprot_is_enabled { } {
	# IRAM0, DPORT_PMS_PRO_IRAM0_0_REG
	if { [get_mmr_bit 0x3f4c1010 0] != 0 } {
		return 1
	}
	# DRAM0, DPORT_PMS_PRO_DRAM0_0_REG
	if { [get_mmr_bit 0x3f4c1028 0] != 0 } {
		return 1
	}
	# PERI1, DPORT_PMS_PRO_DPORT_0_REG
	if { [get_mmr_bit 0x3f4c103c 0] != 0 } {
		return 1
	}
	# PERI2, DPORT_PMS_PRO_AHB_0_REG
	if { [get_mmr_bit 0x3f4c105c 0] != 0 } {
		return 1
	}
	return 0
}

target create $_TARGETNAME esp32s2 -endian little -chain-position $_TAPNAME

$_TARGETNAME configure -event gdb-attach {
	# necessary to auto-probe flash bank when GDB is connected and generate proper memory map
	halt 1000
	if { [esp32s2_memprot_is_enabled] } {
		# 'reset halt' to disable memory protection and allow flasher to work correctly
		echo "Memory protection is enabled. Reset target to disable it..."
		reset halt
	}
}

xtensa maskisr on

$_TARGETNAME configure -event examine-end {
	# Need to enable to set 'semihosting_basedir'
	arm semihosting enable
	arm semihosting_resexit enable
	if { [info exists _SEMIHOST_BASEDIR] } {
		if { $_SEMIHOST_BASEDIR != "" } {
			arm semihosting_basedir $_SEMIHOST_BASEDIR
		}
	}
}

$_TARGETNAME configure -event reset-assert-post { soft_reset_halt }

gdb_breakpoint_override hard

source [find target/xtensa-core-esp32s2.cfg]