riscv-openocd/tcl/target/bluenrg-x.cfg

#
# bluenrg-1/2 and bluenrg-lp devices support only SWD transports.
#

source [find target/swj-dp.tcl]
source [find mem_helper.tcl]

if { [info exists CHIPNAME] } {
   set _CHIPNAME $CHIPNAME
} else {
   set _CHIPNAME bluenrg-1
}

set _ENDIAN little

# Work-area is a space in RAM used for flash programming
# By default use 24kB-256bytes
if { [info exists WORKAREASIZE] } {
   set _WORKAREASIZE $WORKAREASIZE
} else {
   set _WORKAREASIZE 0x5F00
}

adapter speed 4000

swj_newdap $_CHIPNAME cpu -expected-id 0x0bb11477 -expected-id 0x0bc11477
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu

set _TARGETNAME $_CHIPNAME.cpu
set WDOG_VALUE 0
set WDOG_VALUE_SET 0

target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap

$_TARGETNAME configure -work-area-phys 0x20000100 -work-area-size $_WORKAREASIZE -work-area-backup 0

# flash size will be probed
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME bluenrg-x 0 0 0 0 $_TARGETNAME

# In BlueNRG-X reset pin is actually a shutdown (power-off), so define reset as none
reset_config none

if {![using_hla]} {
   # if srst is not fitted use SYSRESETREQ to
   # perform a soft reset
   cortex_m reset_config sysresetreq
}

$_TARGETNAME configure -event halted {
    global WDOG_VALUE
    global WDOG_VALUE_SET
    set _JTAG_IDCODE [mrw 0x40000004]
    if {$_JTAG_IDCODE != 0x0201E041} {
        # Stop watchdog during halt, if enabled. Only Bluenrg-1/2
        set WDOG_VALUE [mrw 0x40700008]
        if [expr ($WDOG_VALUE & (1 << 1))] {
            set WDOG_VALUE_SET 1
            mww 0x40700008 [expr ($WDOG_VALUE & 0xFFFFFFFD)]
        }
    }
}
$_TARGETNAME configure -event resumed {
    global WDOG_VALUE
    global WDOG_VALUE_SET
    set _JTAG_IDCODE [mrw 0x40000004]
    if {$_JTAG_IDCODE != 0x0201E041} {
        if [expr $WDOG_VALUE_SET] {
            # Restore watchdog enable value after resume. Only Bluenrg-1/2
            mww 0x40700008 $WDOG_VALUE
            set WDOG_VALUE_SET 0
           }
   }
}