riscv-openocd/tcl/target/stm32lx_stlink.cfg

#
# STM32lx stlink pseudo target
#

if { [info exists CHIPNAME] == 0 } {
   set CHIPNAME stm32lx
}

if { [info exists CPUTAPID] == 0 } {
   set CPUTAPID 0x2ba01477
}

if { [info exists WORKAREASIZE] == 0 } {
   set WORKAREASIZE 0x2800
}

source [find target/stm32_stlink.cfg]

# Flash base address is known by driver. Flash size will be probed.
#
# Please note that the larger stm32lx targets (256Kb and 384Kb) uses dual
# bank flash. For such targets use target/stm32lx_dual_bank.cfg.
#
# Some samples of ST's stm32lx chips are known to have incorrect flash size
# values programmed in their FLASH_SIZE register. The driver will warn
# for strange values. It is possible to override the flash size probe by
# defining the correct size here. Notice though that it is the size of
# the flash bank
#
# flash bank stm32lx <base> <size> 0 0 <target#> <variant>
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME stm32lx 0 0 0 0 $_TARGETNAME

proc stm32l_enable_HSI {} {
	# Enable HSI as clock source
	echo "STM32L: Enabling HSI"

	# Set HSION in RCC_CR
	mww 0x40023800 0x00000101

	# Set HSI as SYSCLK
	mww 0x40023808 0x00000001
}

$_TARGETNAME configure -event reset-init {
	stm32l_enable_HSI
}