interesting
/
riscv-openocd
mirror of https://github.com/riscv/riscv-openocd.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
riscv-openocd/tcl/target/stm32lx_stlink.cfg

13 lines
229 B
INI
Raw Normal View History

cfg: add stlink pseudo stm32 targets Change-Id: I71253c2090162b1214bbbb37396735bb9128f920 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/334 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2012-01-04 15:48:21 -06:00
#
# STM32lx stlink pseudo target
#
set CHIPNAME stm32lx
cfg: fix incorrect STM32L SW-DP id STM32L ref manual (RM00038 Rev5) states the SW-DP id should be 0x4ba00477. The correct value from silicon is 0x2ba01477 - the typo has been confirmed by ST. Change-Id: Ie35a1f13dc5dedc1b148fb219c6974bfa48b537c Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/441 Tested-by: jenkins Reviewed-by: Peter Stuge <peter@stuge.se>
2012-02-10 05:03:05 -06:00
set CPUTAPID 0x2ba01477
cfg: add stlink pseudo stm32 targets Change-Id: I71253c2090162b1214bbbb37396735bb9128f920 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/334 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2012-01-04 15:48:21 -06:00
set WORKAREASIZE 0x3800
source [find target/stm32_stlink.cfg]
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME stm32lx 0 0 0 0 $_TARGETNAME