riscv-openocd/tcl/target/stm32l4x.cfg

# SPDX-License-Identifier: GPL-2.0-or-later

# script for stm32l4x family

#
# stm32l4 devices support both JTAG and SWD transports.
#
source [find target/swj-dp.tcl]
source [find mem_helper.tcl]

if { [info exists CHIPNAME] } {
   set _CHIPNAME $CHIPNAME
} else {
   set _CHIPNAME stm32l4x
}

set _ENDIAN little

# Work-area is a space in RAM used for flash programming
# By default use 40kB (Available RAM in smallest device STM32L412)
if { [info exists WORKAREASIZE] } {
   set _WORKAREASIZE $WORKAREASIZE
} else {
   set _WORKAREASIZE 0xa000
}

#jtag scan chain
if { [info exists CPUTAPID] } {
   set _CPUTAPID $CPUTAPID
} else {
   if { [using_jtag] } {
      # See STM Document RM0351
      # Section 44.6.3 - corresponds to Cortex-M4 r0p1
      set _CPUTAPID 0x4ba00477
   } {
      set _CPUTAPID 0x2ba01477
   }
}

swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu

if {[using_jtag]} {
   jtag newtap $_CHIPNAME bs -irlen 5
}

set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap

$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0

set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME stm32l4x 0x08000000 0 0 0 $_TARGETNAME
flash bank $_CHIPNAME.otp stm32l4x 0x1fff7000 0 0 0 $_TARGETNAME

if { [info exists QUADSPI] && $QUADSPI } {
   set a [llength [flash list]]
   set _QSPINAME $_CHIPNAME.qspi
   flash bank $_QSPINAME stmqspi 0x90000000 0 0 0 $_TARGETNAME 0xA0001000
} else {
   if { [info exists OCTOSPI1] && $OCTOSPI1 } {
      set a [llength [flash list]]
      set _OCTOSPINAME1 $_CHIPNAME.octospi1
      flash bank $_OCTOSPINAME1 stmqspi 0x90000000 0 0 0 $_TARGETNAME 0xA0001000
   }
   if { [info exists OCTOSPI2] && $OCTOSPI2 } {
      set b [llength [flash list]]
      set _OCTOSPINAME2 $_CHIPNAME.octospi2
      flash bank $_OCTOSPINAME2 stmqspi 0x70000000 0 0 0 $_TARGETNAME 0xA0001400
   }
}

# Common knowledges tells JTAG speed should be <= F_CPU/6.
# F_CPU after reset is MSI 4MHz, so use F_JTAG = 500 kHz to stay on
# the safe side.
#
# Note that there is a pretty wide band where things are
# more or less stable, see http://openocd.zylin.com/#/c/3366/
adapter speed 500

adapter srst delay 100
if {[using_jtag]} {
 jtag_ntrst_delay 100
}

reset_config srst_nogate

if {![using_hla]} {
   # if srst is not fitted use SYSRESETREQ to
   # perform a soft reset
   cortex_m reset_config sysresetreq
}

$_TARGETNAME configure -event examine-end {
	# Enable debug during low power modes (uses more power)
	# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
	mmw 0xE0042004 0x00000007 0

	# Stop watchdog counters during halt
	# DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
	mmw 0xE0042008 0x00001800 0
}

tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0040000

lappend _telnet_autocomplete_skip _proc_pre_enable_$_CHIPNAME.tpiu
proc _proc_pre_enable_$_CHIPNAME.tpiu {_chipname} {
	targets $_chipname.cpu

	if { [$_chipname.tpiu cget -protocol] eq "sync" } {
		switch [$_chipname.tpiu cget -port-width] {
			1 {
				# Set TRACE_IOEN; TRACE_MODE to sync 1 bit; GPIOE[2-3] to AF0
				mmw 0xE0042004 0x00000060 0x000000c0
				mmw 0x48001020 0x00000000 0x0000ff00
				mmw 0x48001000 0x000000a0 0x000000f0
				mmw 0x48001008 0x000000f0 0x00000000
			  }
			2 {
				# Set TRACE_IOEN; TRACE_MODE to sync 2 bit; GPIOE[2-4] to AF0
				mmw 0xE0042004 0x000000a0 0x000000c0
				mmw 0x48001020 0x00000000 0x000fff00
				mmw 0x48001000 0x000002a0 0x000003f0
				mmw 0x48001008 0x000003f0 0x00000000
			  }
			4 {
				# Set TRACE_IOEN; TRACE_MODE to sync 4 bit; GPIOE[2-6] to AF0
				mmw 0xE0042004 0x000000e0 0x000000c0
				mmw 0x48001020 0x00000000 0x0fffff00
				mmw 0x48001000 0x00002aa0 0x00003ff0
				mmw 0x48001008 0x00003ff0 0x00000000
			  }
		}
	} else {
		# Set TRACE_IOEN; TRACE_MODE to async
		mmw 0xE0042004 0x00000020 0x000000c0
	}
}

$_CHIPNAME.tpiu configure -event pre-enable "_proc_pre_enable_$_CHIPNAME.tpiu $_CHIPNAME"

$_TARGETNAME configure -event reset-init {
	# CPU comes out of reset with MSI_ON | MSI_RDY | MSI Range 6 (4 MHz).
	# Use MSI 24 MHz clock, compliant even with VOS == 2.
	# 3 WS compliant with VOS == 2 and 24 MHz.
	mww 0x40022000 0x00000103   ;# FLASH_ACR = PRFTBE | 3(Latency)
	mww 0x40021000 0x00000099   ;# RCC_CR = MSI_ON | MSIRGSEL | MSI Range 9

	# Boost JTAG frequency
	adapter speed 4000
}

$_TARGETNAME configure -event reset-start {
	# Reset clock is MSI (4 MHz)
	adapter speed 500
}