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riscv-openocd/tcl/target/ti_tms570.cfg

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tcl/target: add SPDX tag For historical reasons, no license information was added to the tcl files. This makes trivial adding the SPDX tag through script: fgrep -rL SPDX tcl/ target| while read a;do \ sed -i '1{i# SPDX-License-Identifier: GPL-2.0-or-later\n }' $a;done With no specific license information from the author, let's extend the OpenOCD project license GPL-2.0-or-later to the files. Change-Id: I7b2610300b24cccd07bfa6fb5f1266970d5d3a1b Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/7027 Tested-by: jenkins
2022-06-12 16:42:27 -05:00
# SPDX-License-Identifier: GPL-2.0-or-later
tcl: replace the deprecated commands with "adapter ..." Avoid annoying "deprecated" messages while running the scripts distributed with OpenOCD code. Change automatically created with commands sed -i 's/adapter_khz/adapter speed/g' $(find tcl/ -type f) sed -i 's/adapter_nsrst_delay/adapter srst delay/g' $(find tcl/ -type f) sed -i 's/adapter_nsrst_assert_width/adapter srst pulse_width/g' $(find tcl/ -type f) Minor indentation issue fixed manually in tcl/board/at91sam9g20-ek.cfg tcl/target/at91sam9260_ext_RAM_ext_flash.cfg Change-Id: I425fd56c0c88cd6b06124621306eeb89166dfe71 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5284 Tested-by: jenkins Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
2019-08-23 08:51:00 -05:00
adapter speed 1500
add TI TMS570 support scripts Add support for the TMS570 Cortex-R4 MCU from TI and their USB stick development kit, TMDX570LS31USB. Tested attaching, reset/halt/run, and reading and writing memory and registers. Change-Id: I12d779cef0c2b834f9bcf722307f35677cc4bd8f Signed-off-by: Andrey Yurovsky <yurovsky@gmail.com> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Reviewed-on: http://openocd.zylin.com/1788 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2013-10-31 01:32:40 -05:00
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME tms570
}
if { [info exists ENDIAN] } {
set _ENDIAN $ENDIAN
} else {
set _ENDIAN big
}
# TMS570 has an ICEpick-C on which we need the router commands.
source [find target/icepick.cfg]
# Main DAP
TI TMS570 USB Kit board config Split TMS570 target into LS31/LS21 and LS20/LS10 targets. Board for the TMS570LS20SUSB Kit, which uses the TMS570 Cortex-R4 MCU from TI. Tested attaching. Change-Id: I1a69ac1ed800d0d6b7f9860c19cbd149e3e47620 Signed-off-by: Alex Ray <a@machinaut.com> Reviewed-on: http://openocd.zylin.com/2089 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2014-04-04 01:14:37 -05:00
# DAP_TAPID should be set before source-ing this file
add TI TMS570 support scripts Add support for the TMS570 Cortex-R4 MCU from TI and their USB stick development kit, TMDX570LS31USB. Tested attaching, reset/halt/run, and reading and writing memory and registers. Change-Id: I12d779cef0c2b834f9bcf722307f35677cc4bd8f Signed-off-by: Andrey Yurovsky <yurovsky@gmail.com> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Reviewed-on: http://openocd.zylin.com/1788 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2013-10-31 01:32:40 -05:00
if { [info exists DAP_TAPID] } {
set _DAP_TAPID $DAP_TAPID
}
tcl/target: Add support for TMS570LC43xx Added support for TMS570LC43xx series parts. This uses the pre-existing ti_tms570.cfg parent config. In ti_tms570.cfg, dbgbase was changed. Note 1: Based on the following TI E2E post, the previous dbgbase was wrong and the new value isn't due to a difference in parts. Link: https://e2e.ti.com/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/1106954/tms570ls3137-debugging-with-openocd Note 2: Both the previous dbgbase and the one suggested in the TI E2E post have the 2 LSB set. In the current version of OpenOCD, this will cause cortex_a_read_cpu_memory_fast and cortex_a_write_cpu_memory_fast to fail due to an alignment checks in mem_ap_<read/write>_buf_noincr()->mem_ap_<read/write>(). In all other uses of dbgbase for arm cortex parts, the 2 LSB are masked and ignored. Change-Id: Ic936722e5a4cfc7161b0df1fe3325ee12fd901c6 Signed-off-by: Phil Kirkpatrick <p.kirkpatrick@reflexaerospace.com> Reviewed-on: https://review.openocd.org/c/openocd/+/7682 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-05-09 04:04:24 -05:00
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -disable -ignore-version
tcl/target: ti_tms570.cfg restructure dap support ti_tms570 was probably omitted in commit 2231da8ec4e7d7ae9b652f3dd1a7104f5a110f3f Change-Id: Idd4828fd5ea3641bda6c73c7f07a598c1e512ef6 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/4762 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-11-12 05:13:34 -06:00
jtag configure $_CHIPNAME.cpu -event tap-enable "icepick_c_tapenable $_CHIPNAME.jrc 0"
add TI TMS570 support scripts Add support for the TMS570 Cortex-R4 MCU from TI and their USB stick development kit, TMDX570LS31USB. Tested attaching, reset/halt/run, and reading and writing memory and registers. Change-Id: I12d779cef0c2b834f9bcf722307f35677cc4bd8f Signed-off-by: Andrey Yurovsky <yurovsky@gmail.com> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Reviewed-on: http://openocd.zylin.com/1788 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2013-10-31 01:32:40 -05:00
# ICEpick-C (JTAG route controller)
TI TMS570 USB Kit board config Split TMS570 target into LS31/LS21 and LS20/LS10 targets. Board for the TMS570LS20SUSB Kit, which uses the TMS570 Cortex-R4 MCU from TI. Tested attaching. Change-Id: I1a69ac1ed800d0d6b7f9860c19cbd149e3e47620 Signed-off-by: Alex Ray <a@machinaut.com> Reviewed-on: http://openocd.zylin.com/2089 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2014-04-04 01:14:37 -05:00
# JRC_TAPID should be set before source-ing this file
add TI TMS570 support scripts Add support for the TMS570 Cortex-R4 MCU from TI and their USB stick development kit, TMDX570LS31USB. Tested attaching, reset/halt/run, and reading and writing memory and registers. Change-Id: I12d779cef0c2b834f9bcf722307f35677cc4bd8f Signed-off-by: Andrey Yurovsky <yurovsky@gmail.com> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Reviewed-on: http://openocd.zylin.com/1788 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2013-10-31 01:32:40 -05:00
if { [info exists JRC_TAPID] } {
set _JRC_TAPID $JRC_TAPID
}
target/ti_tms570.cfg: added several JTAG IDs for TMS570LS family from TI datasheets for whole cortex-r4 family added JTAG IDs TMS570LS1227 16- and 32-Bit RISC Flash Microcontroller (Rev. A) http://www.ti.com/lit/pdf/spns192 0x0B95502F 16/32-Bit RISC Flash Microcontroller, TMS5703137-EP (Rev. B) http://www.ti.com/lit/pdf/spns230 0x0D8A002F 0x2D8A002F 0x3D8A002F RM48L952 16- and 32-Bit RISC Flash Microcontroller (Rev. B) http://www.ti.com/lit/pdf/spns177 0x0D8A002F 0x2D8A002F 0x3D8A002F RM46L852 16- and 32-BIT RISC Flash Microcontroller (Rev. A) http://www.ti.com/lit/pdf/spns185 0x0B95502F RM48Lx30 16- and 32-Bit RISC Flash Microcontroller (Rev. A) http://www.ti.com/lit/pdf/spns176 0x0B8A002F 0x2B8A002F 0x3B8A002F RM46Lx30 16- and 32-BIT RISC Flash Microcontroller (Rev. A) http://www.ti.com/lit/pdf/spns182 0x0B95502F RM46Lx50 16- and 32-BIT RISC Flash Microcontroller (Rev. A) http://www.ti.com/lit/pdf/spns184 0x0B95502F TMS570LS04x/03x 16- and 32-BIT RISC Flash Microcontroller (Rev. A) http://www.ti.com/lit/pdf/spns186 0x0B97102F RM42L432 16- and 32-BIT RISC Flash Microcontroller (Rev. A) http://www.ti.com/lit/pdf/spns180 0x0B97102F RM46Lx40 16- and 32-BIT RISC Flash Microcontroller (Rev. A) http://www.ti.com/lit/pdf/ 0x0B95502F TMS570LS12x5 16- and 32-BIT RISC Flash Microcontroller (Rev. A) http://www.ti.com/lit/pdf/spns191 0x0B95502F RM48Lx40 16- and 32-Bit RISC Flash Microcontroller (Rev. A) http://www.ti.com/lit/pdf/spns175 0x0B8A002F 0x2B8A002F 0x3B8A002F TMS570LS31x4/21x4 16- and 32-Bit RISC Flash Microcontroller (Rev. A) http://www.ti.com/lit/pdf/spns165 0x0B8A002F 0x2B8A002F 0x3B8A002F TMS570LS20216/20206/10216/10206/10116/10106 16/32-Bit RISC Flash Microcontroller (Rev. F) http://www.ti.com/lit/pdf/spns141 0x0B7B302F TMS570LS31x5/21x5 16- and 32-Bit RISC Flash Microcontroller (Rev. B) http://www.ti.com/lit/pdf/spns164 0x0B8A002F 0x2B8A002F 0x3B8A002F RM48Lx50 16- and 32-Bit RISC Flash Microcontroller (Rev. A) http://www.ti.com/lit/pdf/spns174 0x0B8A002F 0x2B8A002F 0x3B8A002F TMS570LS3137 16- and 32-Bit RISC Flash Microcontroller (Rev. B) http://www.ti.com/lit/pdf/spns162 0x0B8A002F 0x2B8A002F 0x3B8A002F TMS570LS12x4 16- and 32-BIT RISC Flash Microcontroller (Rev. A) http://www.ti.com/lit/pdf/spns190 0x0B95502F TMS570LS1115 16- and 32-Bit RISC Flash Microcontroller (Rev. A) http://www.ti.com/lit/pdf/spns189 0x0B95502F TMS570LS11x4 16- and 32-BIT RISC Flash Microcontroller (Rev. A) http://www.ti.com/lit/pdf/spns188 0x0B95502F Change-Id: Idf53a44851e1bb4bde4a74c64b65d4411e56da7c Signed-off-by: Jiri Kastner <cz172638@gmail.com> Tested-by: Jiri Kastner <cz172638@gmail.com> Reviewed-on: http://openocd.zylin.com/2123 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2014-05-02 07:55:36 -05:00
set _JRC_TAPID2 0x0B7B302F
set _JRC_TAPID3 0x0B95502F
set _JRC_TAPID4 0x0B97102F
set _JRC_TAPID5 0x0D8A002F
tcl/target: Add support for TMS570LC43xx Added support for TMS570LC43xx series parts. This uses the pre-existing ti_tms570.cfg parent config. In ti_tms570.cfg, dbgbase was changed. Note 1: Based on the following TI E2E post, the previous dbgbase was wrong and the new value isn't due to a difference in parts. Link: https://e2e.ti.com/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/1106954/tms570ls3137-debugging-with-openocd Note 2: Both the previous dbgbase and the one suggested in the TI E2E post have the 2 LSB set. In the current version of OpenOCD, this will cause cortex_a_read_cpu_memory_fast and cortex_a_write_cpu_memory_fast to fail due to an alignment checks in mem_ap_<read/write>_buf_noincr()->mem_ap_<read/write>(). In all other uses of dbgbase for arm cortex parts, the 2 LSB are masked and ignored. Change-Id: Ic936722e5a4cfc7161b0df1fe3325ee12fd901c6 Signed-off-by: Phil Kirkpatrick <p.kirkpatrick@reflexaerospace.com> Reviewed-on: https://review.openocd.org/c/openocd/+/7682 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-05-09 04:04:24 -05:00
set _JRC_TAPID6 0x0B8A002F
target/ti_tms570.cfg: added several JTAG IDs for TMS570LS family from TI datasheets for whole cortex-r4 family added JTAG IDs TMS570LS1227 16- and 32-Bit RISC Flash Microcontroller (Rev. A) http://www.ti.com/lit/pdf/spns192 0x0B95502F 16/32-Bit RISC Flash Microcontroller, TMS5703137-EP (Rev. B) http://www.ti.com/lit/pdf/spns230 0x0D8A002F 0x2D8A002F 0x3D8A002F RM48L952 16- and 32-Bit RISC Flash Microcontroller (Rev. B) http://www.ti.com/lit/pdf/spns177 0x0D8A002F 0x2D8A002F 0x3D8A002F RM46L852 16- and 32-BIT RISC Flash Microcontroller (Rev. A) http://www.ti.com/lit/pdf/spns185 0x0B95502F RM48Lx30 16- and 32-Bit RISC Flash Microcontroller (Rev. A) http://www.ti.com/lit/pdf/spns176 0x0B8A002F 0x2B8A002F 0x3B8A002F RM46Lx30 16- and 32-BIT RISC Flash Microcontroller (Rev. A) http://www.ti.com/lit/pdf/spns182 0x0B95502F RM46Lx50 16- and 32-BIT RISC Flash Microcontroller (Rev. A) http://www.ti.com/lit/pdf/spns184 0x0B95502F TMS570LS04x/03x 16- and 32-BIT RISC Flash Microcontroller (Rev. A) http://www.ti.com/lit/pdf/spns186 0x0B97102F RM42L432 16- and 32-BIT RISC Flash Microcontroller (Rev. A) http://www.ti.com/lit/pdf/spns180 0x0B97102F RM46Lx40 16- and 32-BIT RISC Flash Microcontroller (Rev. A) http://www.ti.com/lit/pdf/ 0x0B95502F TMS570LS12x5 16- and 32-BIT RISC Flash Microcontroller (Rev. A) http://www.ti.com/lit/pdf/spns191 0x0B95502F RM48Lx40 16- and 32-Bit RISC Flash Microcontroller (Rev. A) http://www.ti.com/lit/pdf/spns175 0x0B8A002F 0x2B8A002F 0x3B8A002F TMS570LS31x4/21x4 16- and 32-Bit RISC Flash Microcontroller (Rev. A) http://www.ti.com/lit/pdf/spns165 0x0B8A002F 0x2B8A002F 0x3B8A002F TMS570LS20216/20206/10216/10206/10116/10106 16/32-Bit RISC Flash Microcontroller (Rev. F) http://www.ti.com/lit/pdf/spns141 0x0B7B302F TMS570LS31x5/21x5 16- and 32-Bit RISC Flash Microcontroller (Rev. B) http://www.ti.com/lit/pdf/spns164 0x0B8A002F 0x2B8A002F 0x3B8A002F RM48Lx50 16- and 32-Bit RISC Flash Microcontroller (Rev. A) http://www.ti.com/lit/pdf/spns174 0x0B8A002F 0x2B8A002F 0x3B8A002F TMS570LS3137 16- and 32-Bit RISC Flash Microcontroller (Rev. B) http://www.ti.com/lit/pdf/spns162 0x0B8A002F 0x2B8A002F 0x3B8A002F TMS570LS12x4 16- and 32-BIT RISC Flash Microcontroller (Rev. A) http://www.ti.com/lit/pdf/spns190 0x0B95502F TMS570LS1115 16- and 32-Bit RISC Flash Microcontroller (Rev. A) http://www.ti.com/lit/pdf/spns189 0x0B95502F TMS570LS11x4 16- and 32-BIT RISC Flash Microcontroller (Rev. A) http://www.ti.com/lit/pdf/spns188 0x0B95502F Change-Id: Idf53a44851e1bb4bde4a74c64b65d4411e56da7c Signed-off-by: Jiri Kastner <cz172638@gmail.com> Tested-by: Jiri Kastner <cz172638@gmail.com> Reviewed-on: http://openocd.zylin.com/2123 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2014-05-02 07:55:36 -05:00
add TI TMS570 support scripts Add support for the TMS570 Cortex-R4 MCU from TI and their USB stick development kit, TMDX570LS31USB. Tested attaching, reset/halt/run, and reading and writing memory and registers. Change-Id: I12d779cef0c2b834f9bcf722307f35677cc4bd8f Signed-off-by: Andrey Yurovsky <yurovsky@gmail.com> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Reviewed-on: http://openocd.zylin.com/1788 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2013-10-31 01:32:40 -05:00
jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f \
target/ti_tms570.cfg: added several JTAG IDs for TMS570LS family from TI datasheets for whole cortex-r4 family added JTAG IDs TMS570LS1227 16- and 32-Bit RISC Flash Microcontroller (Rev. A) http://www.ti.com/lit/pdf/spns192 0x0B95502F 16/32-Bit RISC Flash Microcontroller, TMS5703137-EP (Rev. B) http://www.ti.com/lit/pdf/spns230 0x0D8A002F 0x2D8A002F 0x3D8A002F RM48L952 16- and 32-Bit RISC Flash Microcontroller (Rev. B) http://www.ti.com/lit/pdf/spns177 0x0D8A002F 0x2D8A002F 0x3D8A002F RM46L852 16- and 32-BIT RISC Flash Microcontroller (Rev. A) http://www.ti.com/lit/pdf/spns185 0x0B95502F RM48Lx30 16- and 32-Bit RISC Flash Microcontroller (Rev. A) http://www.ti.com/lit/pdf/spns176 0x0B8A002F 0x2B8A002F 0x3B8A002F RM46Lx30 16- and 32-BIT RISC Flash Microcontroller (Rev. A) http://www.ti.com/lit/pdf/spns182 0x0B95502F RM46Lx50 16- and 32-BIT RISC Flash Microcontroller (Rev. A) http://www.ti.com/lit/pdf/spns184 0x0B95502F TMS570LS04x/03x 16- and 32-BIT RISC Flash Microcontroller (Rev. A) http://www.ti.com/lit/pdf/spns186 0x0B97102F RM42L432 16- and 32-BIT RISC Flash Microcontroller (Rev. A) http://www.ti.com/lit/pdf/spns180 0x0B97102F RM46Lx40 16- and 32-BIT RISC Flash Microcontroller (Rev. A) http://www.ti.com/lit/pdf/ 0x0B95502F TMS570LS12x5 16- and 32-BIT RISC Flash Microcontroller (Rev. A) http://www.ti.com/lit/pdf/spns191 0x0B95502F RM48Lx40 16- and 32-Bit RISC Flash Microcontroller (Rev. A) http://www.ti.com/lit/pdf/spns175 0x0B8A002F 0x2B8A002F 0x3B8A002F TMS570LS31x4/21x4 16- and 32-Bit RISC Flash Microcontroller (Rev. A) http://www.ti.com/lit/pdf/spns165 0x0B8A002F 0x2B8A002F 0x3B8A002F TMS570LS20216/20206/10216/10206/10116/10106 16/32-Bit RISC Flash Microcontroller (Rev. F) http://www.ti.com/lit/pdf/spns141 0x0B7B302F TMS570LS31x5/21x5 16- and 32-Bit RISC Flash Microcontroller (Rev. B) http://www.ti.com/lit/pdf/spns164 0x0B8A002F 0x2B8A002F 0x3B8A002F RM48Lx50 16- and 32-Bit RISC Flash Microcontroller (Rev. A) http://www.ti.com/lit/pdf/spns174 0x0B8A002F 0x2B8A002F 0x3B8A002F TMS570LS3137 16- and 32-Bit RISC Flash Microcontroller (Rev. B) http://www.ti.com/lit/pdf/spns162 0x0B8A002F 0x2B8A002F 0x3B8A002F TMS570LS12x4 16- and 32-BIT RISC Flash Microcontroller (Rev. A) http://www.ti.com/lit/pdf/spns190 0x0B95502F TMS570LS1115 16- and 32-Bit RISC Flash Microcontroller (Rev. A) http://www.ti.com/lit/pdf/spns189 0x0B95502F TMS570LS11x4 16- and 32-BIT RISC Flash Microcontroller (Rev. A) http://www.ti.com/lit/pdf/spns188 0x0B95502F Change-Id: Idf53a44851e1bb4bde4a74c64b65d4411e56da7c Signed-off-by: Jiri Kastner <cz172638@gmail.com> Tested-by: Jiri Kastner <cz172638@gmail.com> Reviewed-on: http://openocd.zylin.com/2123 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2014-05-02 07:55:36 -05:00
-expected-id $_JRC_TAPID \
-expected-id $_JRC_TAPID2 \
-expected-id $_JRC_TAPID3 \
-expected-id $_JRC_TAPID4 \
-expected-id $_JRC_TAPID5 \
-expected-id $_JRC_TAPID6 \
-ignore-version
tcl/target: ti_tms570.cfg restructure dap support ti_tms570 was probably omitted in commit 2231da8ec4e7d7ae9b652f3dd1a7104f5a110f3f Change-Id: Idd4828fd5ea3641bda6c73c7f07a598c1e512ef6 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/4762 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-11-12 05:13:34 -06:00
jtag configure $_CHIPNAME.jrc -event setup "jtag tapenable $_CHIPNAME.cpu"
add TI TMS570 support scripts Add support for the TMS570 Cortex-R4 MCU from TI and their USB stick development kit, TMDX570LS31USB. Tested attaching, reset/halt/run, and reading and writing memory and registers. Change-Id: I12d779cef0c2b834f9bcf722307f35677cc4bd8f Signed-off-by: Andrey Yurovsky <yurovsky@gmail.com> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Reviewed-on: http://openocd.zylin.com/1788 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2013-10-31 01:32:40 -05:00
jtag configure $_CHIPNAME.jrc -event post-reset "runtest 100"
tcl/target: ti_tms570.cfg restructure dap support ti_tms570 was probably omitted in commit 2231da8ec4e7d7ae9b652f3dd1a7104f5a110f3f Change-Id: Idd4828fd5ea3641bda6c73c7f07a598c1e512ef6 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/4762 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-11-12 05:13:34 -06:00
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
Fix spelling of ARM Cortex It's Cortex-Xn, not Cortex Xn or cortex xn or cortex-xn or CORTEX-Xn or CortexXn. Further it's Cortex-M0+, not M0plus. Cf. http://www.arm.com/products/processors/index.php Consistently write it the official way, so that it stops propagating. Originally spotted in the documentation, it mainly affects code comments but also Atmel SAM3/SAM4/SAMV, NiietCM4 and SiM3x flash driver output. Found via: git grep -i "Cortex " git grep -i "Cortex-" | grep -v "Cortex-" | grep -v ".cpu" git grep -i "CortexM" Change-Id: Ic7b6ca85253e027f6f0f751c628d1a2a391fe914 Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-on: http://openocd.zylin.com/3483 Tested-by: jenkins Reviewed-by: Marc Schink <openocd-dev@marcschink.de> Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2016-05-14 13:21:49 -05:00
# Cortex-R4 target
add TI TMS570 support scripts Add support for the TMS570 Cortex-R4 MCU from TI and their USB stick development kit, TMDX570LS31USB. Tested attaching, reset/halt/run, and reading and writing memory and registers. Change-Id: I12d779cef0c2b834f9bcf722307f35677cc4bd8f Signed-off-by: Andrey Yurovsky <yurovsky@gmail.com> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Reviewed-on: http://openocd.zylin.com/1788 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2013-10-31 01:32:40 -05:00
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_r4 -endian $_ENDIAN \
tcl/target: Add support for TMS570LC43xx Added support for TMS570LC43xx series parts. This uses the pre-existing ti_tms570.cfg parent config. In ti_tms570.cfg, dbgbase was changed. Note 1: Based on the following TI E2E post, the previous dbgbase was wrong and the new value isn't due to a difference in parts. Link: https://e2e.ti.com/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/1106954/tms570ls3137-debugging-with-openocd Note 2: Both the previous dbgbase and the one suggested in the TI E2E post have the 2 LSB set. In the current version of OpenOCD, this will cause cortex_a_read_cpu_memory_fast and cortex_a_write_cpu_memory_fast to fail due to an alignment checks in mem_ap_<read/write>_buf_noincr()->mem_ap_<read/write>(). In all other uses of dbgbase for arm cortex parts, the 2 LSB are masked and ignored. Change-Id: Ic936722e5a4cfc7161b0df1fe3325ee12fd901c6 Signed-off-by: Phil Kirkpatrick <p.kirkpatrick@reflexaerospace.com> Reviewed-on: https://review.openocd.org/c/openocd/+/7682 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-05-09 04:04:24 -05:00
-dap $_CHIPNAME.dap -coreid 0 -dbgbase 0x80001000
add TI TMS570 support scripts Add support for the TMS570 Cortex-R4 MCU from TI and their USB stick development kit, TMDX570LS31USB. Tested attaching, reset/halt/run, and reading and writing memory and registers. Change-Id: I12d779cef0c2b834f9bcf722307f35677cc4bd8f Signed-off-by: Andrey Yurovsky <yurovsky@gmail.com> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Reviewed-on: http://openocd.zylin.com/1788 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2013-10-31 01:32:40 -05:00
cortex_a: fix endiannes issues on TI TMS570 The TI TMS470 and TMS570 series of processors are BE-32 processors, despite BE-32 not being supported by ARM in the Cortex-R4 core. TI hacked in BE-32 support, which requires odd swizzling in OpenOCD to make memory reads and writes function correctly. In particular, without this change, OpenOCD word reads and writes had the bytes reversed, and halfword and byte packed reads were reading garbage. In my testing, this change fixes these problems. Change-Id: I21dd30f4b9003f20fcc85f674ab833407bb61f74 Signed-off-by: Seth LaForge <sethml@google.com> Reviewed-on: http://openocd.zylin.com/2064 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com> Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2014-04-01 12:26:32 -05:00
# TMS570 uses quirky BE-32 mode
tcl/target: ti_tms570.cfg restructure dap support ti_tms570 was probably omitted in commit 2231da8ec4e7d7ae9b652f3dd1a7104f5a110f3f Change-Id: Idd4828fd5ea3641bda6c73c7f07a598c1e512ef6 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/4762 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-11-12 05:13:34 -06:00
$_CHIPNAME.dap ti_be_32_quirks 1
cortex_a: fix endiannes issues on TI TMS570 The TI TMS470 and TMS570 series of processors are BE-32 processors, despite BE-32 not being supported by ARM in the Cortex-R4 core. TI hacked in BE-32 support, which requires odd swizzling in OpenOCD to make memory reads and writes function correctly. In particular, without this change, OpenOCD word reads and writes had the bytes reversed, and halfword and byte packed reads were reading garbage. In my testing, this change fixes these problems. Change-Id: I21dd30f4b9003f20fcc85f674ab833407bb61f74 Signed-off-by: Seth LaForge <sethml@google.com> Reviewed-on: http://openocd.zylin.com/2064 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com> Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2014-04-01 12:26:32 -05:00
add TI TMS570 support scripts Add support for the TMS570 Cortex-R4 MCU from TI and their USB stick development kit, TMDX570LS31USB. Tested attaching, reset/halt/run, and reading and writing memory and registers. Change-Id: I12d779cef0c2b834f9bcf722307f35677cc4bd8f Signed-off-by: Andrey Yurovsky <yurovsky@gmail.com> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Reviewed-on: http://openocd.zylin.com/1788 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2013-10-31 01:32:40 -05:00
$_TARGETNAME configure -event "reset-assert" {
global _CHIPNAME
# assert warm system reset through ICEPick
icepick_c_wreset $_CHIPNAME.jrc
}