riscv-openocd/tcl/target/str710.cfg

#start slow, speed up after reset
jtag_khz 10

if { [info exists CHIPNAME] } {
   set  _CHIPNAME $CHIPNAME
} else {
   set  _CHIPNAME str710
}

if { [info exists ENDIAN] } {
   set  _ENDIAN $ENDIAN
} else {
   set  _ENDIAN little
}

if { [info exists CPUTAPID] } {
   set  _CPUTAPID $CPUTAPID
} else {
   set  _CPUTAPID 0x3f0f0f0f
}

#use combined on interfaces or targets that can't set TRST/SRST separately
reset_config trst_and_srst srst_pulls_trst

#jtag scan chain

jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0x0f -expected-id $_CPUTAPID

set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm7tdmi

$_TARGETNAME configure -event reset-start { jtag_khz 10 }
$_TARGETNAME configure -event reset-init { jtag_khz 6000 }
$_TARGETNAME configure -event gdb-flash-erase-start {
	flash protect 0 0 7 off
	flash protect 1 0 1 off
}

$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x2000C000 -work-area-size 0x4000 -work-area-backup 0

#flash bank str7x <base> <size> 0 0 <target#> <variant>
flash bank str7x 0x40000000 0x00040000 0 0 0 STR71x
flash bank str7x 0x400C0000 0x00004000 0 0 0 STR71x

# For more information about the configuration files, take a look at:
# openocd.texi