riscv-openocd/tcl/target/str912.cfg

# script for str9

if { [info exists CHIPNAME] } {
   set  _CHIPNAME $CHIPNAME
} else {
   set  _CHIPNAME str912
}

if { [info exists ENDIAN] } {
   set  _ENDIAN $ENDIAN
} else {
   set  _ENDIAN little
}

# jtag speed. We need to stick to 16kHz until we've finished reset.
jtag_rclk 16

adapter_nsrst_delay 100
jtag_ntrst_delay 100

#use combined on interfaces or targets that can't set TRST/SRST separately
reset_config trst_and_srst

if { [info exists FLASHTAPID ] } {
   set _FLASHTAPID $FLASHTAPID
} else {
   set _FLASHTAPID 0x04570041
}
jtag newtap $_CHIPNAME flash -irlen 8 -ircapture 0x1 -irmask 0x1 -expected-id $_FLASHTAPID

if { [info exists CPUTAPID ] } {
   set _CPUTAPID $CPUTAPID
} else {
   set _CPUTAPID 0x25966041
}
jtag newtap $_CHIPNAME cpu   -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID


if { [info exists BSTAPID ] } {
   set _BSTAPID $BSTAPID
} else {
   set _BSTAPID 0x1457f041
}
jtag newtap $_CHIPNAME bs    -irlen 5 -ircapture 0x1 -irmask 0x1 -expected-id $_BSTAPID

set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME arm966e -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm966e

$_TARGETNAME configure -event reset-start { jtag_rclk 16 }

$_TARGETNAME configure -event reset-init {
	# We can increase speed now that we know the target is halted.
	#jtag_rclk 3000

	# -- Enable 96K RAM
	# PFQBC enabled / DTCM & AHB wait-states disabled
	mww 0x5C002034 0x0191

	str9x flash_config 0 4 2 0 0x80000
	flash protect 0 0 7 off
}

$_TARGETNAME configure -work-area-phys 0x50000000 -work-area-size 16384 -work-area-backup 0

#flash bank str9x <base> <size> 0 0 <target#> <variant>
set _FLASHNAME $_CHIPNAME.flash0
flash bank $_FLASHNAME str9x 0x00000000 0x00080000 0 0 $_TARGETNAME
set _FLASHNAME $_CHIPNAME.flash1
flash bank $_FLASHNAME str9x 0x00080000 0x00008000 0 0 $_TARGETNAME

# For more information about the configuration files, take a look at:
# openocd.texi