2015-07-01 04:18:46 -05:00
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#!/usr/bin/python3
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#
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# Copyright (C) 2015 Robert Jordens <jordens@gmail.com>
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation; either version 2 of the License, or
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# (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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2017-08-08 11:16:35 -05:00
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import unittest
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import migen as mg
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import migen.build.generic_platform as mb
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from migen.genlib import io
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2015-12-21 14:36:14 -06:00
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from migen.build import xilinx
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2015-07-01 04:18:46 -05:00
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"""
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This migen script produces proxy bitstreams to allow programming SPI flashes
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2015-12-21 14:36:14 -06:00
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behind FPGAs.
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Bitstream binaries built with this script are available at:
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https://github.com/jordens/bscan_spi_bitstreams
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2015-07-01 04:18:46 -05:00
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2017-08-08 11:16:35 -05:00
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A JTAG2SPI transfer consists of:
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1. an arbitrary number of 0 bits (from BYPASS registers in front of the
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JTAG2SPI DR)
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2. a marker bit (1) indicating the start of the JTAG2SPI transaction
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3. 32 bits (big endian) describing the length of the SPI transaction
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4. a number of SPI clock cycles (corresponding to 3.) with CS_N asserted
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5. an arbitrary number of cycles (to shift MISO/TDO data through subsequent
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BYPASS registers)
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Notes:
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* The JTAG2SPI DR is 1 bit long (due to different sampling edges of
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{MISO,MOSI}/{TDO,TDI}).
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* MOSI is TDI with half a cycle delay.
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* TDO is MISO with half a cycle delay.
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* CAPTURE-DR needs to be performed before SHIFT-DR on the BYPASSed TAPs in
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JTAG chain to clear the BYPASS registers to 0.
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2015-07-01 04:18:46 -05:00
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https://github.com/m-labs/migen
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"""
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2017-08-08 11:16:35 -05:00
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class JTAG2SPI(mg.Module):
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def __init__(self, spi=None, bits=32):
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self.jtag = mg.Record([
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("sel", 1),
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("shift", 1),
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("capture", 1),
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("tck", 1),
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("tdi", 1),
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("tdo", 1),
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])
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self.cs_n = mg.TSTriple()
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self.clk = mg.TSTriple()
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self.mosi = mg.TSTriple()
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self.miso = mg.TSTriple()
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# # #
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self.cs_n.o.reset = mg.Constant(1)
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self.mosi.o.reset_less = True
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bits = mg.Signal(bits, reset_less=True)
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head = mg.Signal(max=len(bits), reset=len(bits) - 1)
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self.clock_domains.cd_sys = mg.ClockDomain()
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self.submodules.fsm = mg.FSM("IDLE")
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if spi is not None:
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self.specials += [
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self.cs_n.get_tristate(spi.cs_n),
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self.mosi.get_tristate(spi.mosi),
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self.miso.get_tristate(spi.miso),
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]
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if hasattr(spi, "clk"): # 7 Series drive it fixed
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self.specials += self.clk.get_tristate(spi.clk)
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# self.specials += io.DDROutput(1, 0, spi.clk, self.clk.o)
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self.comb += [
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self.cd_sys.rst.eq(self.jtag.sel & self.jtag.capture),
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self.cd_sys.clk.eq(self.jtag.tck),
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self.cs_n.oe.eq(self.jtag.sel),
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self.clk.oe.eq(self.jtag.sel),
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self.mosi.oe.eq(self.jtag.sel),
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self.miso.oe.eq(0),
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# Do not suppress CLK toggles outside CS_N asserted.
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# Xilinx USRCCLK0 requires three dummy cycles to do anything
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# https://www.xilinx.com/support/answers/52626.html
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# This is fine since CS_N changes only on falling CLK.
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self.clk.o.eq(~self.jtag.tck),
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self.jtag.tdo.eq(self.miso.i),
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]
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# Latency calculation (in half cycles):
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# 0 (falling TCK, rising CLK):
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# JTAG adapter: set TDI
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# 1 (rising TCK, falling CLK):
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# JTAG2SPI: sample TDI -> set MOSI
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# SPI: set MISO
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# 2 (falling TCK, rising CLK):
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# SPI: sample MOSI
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# JTAG2SPI (BSCAN primitive): sample MISO -> set TDO
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# 3 (rising TCK, falling CLK):
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# JTAG adapter: sample TDO
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self.fsm.act("IDLE",
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mg.If(self.jtag.tdi & self.jtag.sel & self.jtag.shift,
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mg.NextState("HEAD")
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)
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)
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self.fsm.act("HEAD",
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mg.If(head == 0,
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mg.NextState("XFER")
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)
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)
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self.fsm.act("XFER",
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mg.If(bits == 0,
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mg.NextState("IDLE")
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),
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)
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self.sync += [
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self.mosi.o.eq(self.jtag.tdi),
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self.cs_n.o.eq(~self.fsm.ongoing("XFER")),
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mg.If(self.fsm.ongoing("HEAD"),
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bits.eq(mg.Cat(self.jtag.tdi, bits)),
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head.eq(head - 1)
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),
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mg.If(self.fsm.ongoing("XFER"),
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bits.eq(bits - 1)
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)
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]
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class JTAG2SPITest(unittest.TestCase):
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def setUp(self):
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self.bits = 8
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self.dut = JTAG2SPI(bits=self.bits)
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def test_instantiate(self):
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pass
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def test_initial_conditions(self):
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def check():
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yield
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self.assertEqual((yield self.dut.cs_n.oe), 0)
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self.assertEqual((yield self.dut.mosi.oe), 0)
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self.assertEqual((yield self.dut.miso.oe), 0)
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self.assertEqual((yield self.dut.clk.oe), 0)
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mg.run_simulation(self.dut, check())
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def test_enable(self):
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def check():
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yield self.dut.jtag.sel.eq(1)
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yield self.dut.jtag.shift.eq(1)
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yield
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self.assertEqual((yield self.dut.cs_n.oe), 1)
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self.assertEqual((yield self.dut.mosi.oe), 1)
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self.assertEqual((yield self.dut.miso.oe), 0)
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self.assertEqual((yield self.dut.clk.oe), 1)
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mg.run_simulation(self.dut, check())
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def run_seq(self, tdi, tdo, spi=None):
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yield self.dut.jtag.sel.eq(1)
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yield
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yield self.dut.jtag.shift.eq(1)
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for di in tdi:
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yield self.dut.jtag.tdi.eq(di)
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yield
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tdo.append((yield self.dut.jtag.tdo))
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if spi is not None:
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v = []
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for k in "cs_n clk mosi miso".split():
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t = getattr(self.dut, k)
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v.append("{}>".format((yield t.o)) if (yield t.oe)
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else "<{}".format((yield t.i)))
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spi.append(" ".join(v))
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yield self.dut.jtag.sel.eq(0)
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yield
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yield self.dut.jtag.shift.eq(0)
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yield
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def test_shift(self):
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bits = 8
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data = 0x81
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tdi = [0, 0, 1] # dummy from BYPASS TAPs and marker
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tdi += [((bits - 1) >> j) & 1 for j in range(self.bits - 1, -1, -1)]
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tdi += [(data >> j) & 1 for j in range(bits)]
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tdi += [0, 0, 0, 0] # dummy from BYPASS TAPs
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tdo = []
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spi = []
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mg.run_simulation(self.dut, self.run_seq(tdi, tdo, spi))
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# print(tdo)
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for l in spi:
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print(l)
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class Spartan3(mg.Module):
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macro = "BSCAN_SPARTAN3"
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toolchain = "ise"
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def __init__(self, platform):
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platform.toolchain.bitgen_opt += " -g compress -g UnusedPin:Pullup"
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self.submodules.j2s = j2s = JTAG2SPI(platform.request("spiflash"))
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self.specials += [
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mg.Instance(
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self.macro,
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o_SHIFT=j2s.jtag.shift, o_SEL1=j2s.jtag.sel,
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o_CAPTURE=j2s.jtag.capture,
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o_DRCK1=j2s.jtag.tck,
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o_TDI=j2s.jtag.tdi, i_TDO1=j2s.jtag.tdo,
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i_TDO2=0),
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]
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platform.add_period_constraint(j2s.jtag.tck, 6)
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class Spartan3A(Spartan3):
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macro = "BSCAN_SPARTAN3A"
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class Spartan6(mg.Module):
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toolchain = "ise"
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def __init__(self, platform):
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platform.toolchain.bitgen_opt += " -g compress -g UnusedPin:Pullup"
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self.submodules.j2s = j2s = JTAG2SPI(platform.request("spiflash"))
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# clk = mg.Signal()
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self.specials += [
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mg.Instance(
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"BSCAN_SPARTAN6", p_JTAG_CHAIN=1,
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o_SHIFT=j2s.jtag.shift, o_SEL=j2s.jtag.sel,
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o_CAPTURE=j2s.jtag.capture,
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o_DRCK=j2s.jtag.tck,
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o_TDI=j2s.jtag.tdi, i_TDO=j2s.jtag.tdo),
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# mg.Instance("BUFG", i_I=clk, o_O=j2s.jtag.tck)
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]
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platform.add_period_constraint(j2s.jtag.tck, 6)
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class Series7(mg.Module):
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toolchain = "vivado"
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def __init__(self, platform):
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platform.toolchain.bitstream_commands.extend([
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"set_property BITSTREAM.GENERAL.COMPRESS True [current_design]",
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"set_property BITSTREAM.CONFIG.UNUSEDPIN Pullnone [current_design]"
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])
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self.submodules.j2s = j2s = JTAG2SPI(platform.request("spiflash"))
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# clk = mg.Signal()
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self.specials += [
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mg.Instance(
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"BSCANE2", p_JTAG_CHAIN=1,
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o_SHIFT=j2s.jtag.shift, o_SEL=j2s.jtag.sel,
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o_CAPTURE=j2s.jtag.capture,
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o_DRCK=j2s.jtag.tck,
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o_TDI=j2s.jtag.tdi, i_TDO=j2s.jtag.tdo),
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mg.Instance(
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"STARTUPE2", i_CLK=0, i_GSR=0, i_GTS=0,
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i_KEYCLEARB=0, i_PACK=1,
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i_USRCCLKO=j2s.clk.o, i_USRCCLKTS=~j2s.clk.oe,
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i_USRDONEO=1, i_USRDONETS=1),
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# mg.Instance("BUFG", i_I=clk, o_O=j2s.jtag.tck)
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]
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platform.add_period_constraint(j2s.jtag.tck, 6)
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try:
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self.comb += [
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platform.request("user_sma_gpio_p").eq(j2s.cs_n.i),
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platform.request("user_sma_gpio_n").eq(j2s.clk.o),
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platform.request("user_sma_clock_p").eq(j2s.mosi.o),
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platform.request("user_sma_clock_n").eq(j2s.miso.i),
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]
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except mb.ConstraintError:
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pass
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class Ultrascale(mg.Module):
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toolchain = "vivado"
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def __init__(self, platform):
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platform.toolchain.bitstream_commands.extend([
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"set_property BITSTREAM.GENERAL.COMPRESS True [current_design]",
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"set_property BITSTREAM.CONFIG.UNUSEDPIN Pullnone [current_design]",
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])
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self.submodules.j2s0 = j2s0 = JTAG2SPI()
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self.submodules.j2s1 = j2s1 = JTAG2SPI(platform.request("spiflash"))
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di = mg.Signal(4)
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self.comb += mg.Cat(j2s0.mosi.i, j2s0.miso.i).eq(di)
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self.specials += [
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mg.Instance("BSCANE2", p_JTAG_CHAIN=1,
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o_SHIFT=j2s0.jtag.shift, o_SEL=j2s0.jtag.sel,
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o_CAPTURE=j2s0.jtag.capture,
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o_DRCK=j2s0.jtag.tck,
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o_TDI=j2s0.jtag.tdi, i_TDO=j2s0.jtag.tdo),
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mg.Instance("BSCANE2", p_JTAG_CHAIN=2,
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o_SHIFT=j2s1.jtag.shift, o_SEL=j2s1.jtag.sel,
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o_CAPTURE=j2s1.jtag.capture,
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o_DRCK=j2s1.jtag.tck,
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o_TDI=j2s1.jtag.tdi, i_TDO=j2s1.jtag.tdo),
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mg.Instance("STARTUPE3", i_GSR=0, i_GTS=0,
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i_KEYCLEARB=0, i_PACK=1,
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i_USRDONEO=1, i_USRDONETS=1,
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i_USRCCLKO=mg.Mux(j2s0.clk.oe, j2s0.clk.o, j2s1.clk.o),
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i_USRCCLKTS=~(j2s0.clk.oe | j2s1.clk.oe),
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i_FCSBO=j2s0.cs_n.o, i_FCSBTS=~j2s0.cs_n.oe,
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o_DI=di,
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i_DO=mg.Cat(j2s0.mosi.o, j2s0.miso.o, 0, 0),
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i_DTS=mg.Cat(~j2s0.mosi.oe, ~j2s0.miso.oe, 1, 1))
|
|
|
|
]
|
|
|
|
platform.add_period_constraint(j2s0.jtag.tck, 6)
|
|
|
|
platform.add_period_constraint(j2s1.jtag.tck, 6)
|
2015-07-01 04:18:46 -05:00
|
|
|
|
|
|
|
|
2015-12-21 14:36:14 -06:00
|
|
|
class XilinxBscanSpi(xilinx.XilinxPlatform):
|
|
|
|
packages = {
|
|
|
|
# (package-speedgrade, id): [cs_n, clk, mosi, miso, *pullups]
|
|
|
|
("cp132", 1): ["M2", "N12", "N2", "N8"],
|
|
|
|
("fg320", 1): ["U3", "U16", "T4", "N10"],
|
|
|
|
("fg320", 2): ["V3", "U16", "T11", "V16"],
|
|
|
|
("fg484", 1): ["Y4", "AA20", "AB14", "AB20"],
|
|
|
|
("fgg484", 1): ["Y4", "AA20", "AB14", "AB20"],
|
|
|
|
("fgg400", 1): ["Y2", "Y19", "W12", "W18"],
|
|
|
|
("ftg256", 1): ["T2", "R14", "P10", "T14"],
|
|
|
|
("ft256", 1): ["T2", "R14", "P10", "T14"],
|
|
|
|
("fg400", 1): ["Y2", "Y19", "W12", "W18"],
|
|
|
|
("cs484", 1): ["U7", "V17", "V13", "W17"],
|
|
|
|
("qg144-2", 1): ["P38", "P70", "P64", "P65", "P62", "P61"],
|
|
|
|
("cpg196-2", 1): ["P2", "N13", "P11", "N11", "N10", "P10"],
|
|
|
|
("cpg236-1", 1): ["K19", None, "D18", "D19", "G18", "F18"],
|
|
|
|
("csg484-2", 1): ["AB5", "W17", "AB17", "Y17", "V13", "W13"],
|
|
|
|
("csg324-2", 1): ["V3", "R15", "T13", "R13", "T14", "V14"],
|
|
|
|
("csg324-1", 1): ["L13", None, "K17", "K18", "L14", "M14"],
|
|
|
|
("fbg484-1", 1): ["T19", None, "P22", "R22", "P21", "R21"],
|
|
|
|
("fbg484-1", 2): ["L16", None, "H18", "H19", "G18", "F19"],
|
|
|
|
("fbg676-1", 1): ["C23", None, "B24", "A25", "B22", "A22"],
|
|
|
|
("ffg901-1", 1): ["V26", None, "R30", "T30", "R28", "T28"],
|
2017-08-08 11:16:35 -05:00
|
|
|
("ffg900-1", 1): ["U19", None, "P24", "R25", "R20", "R21"],
|
2015-12-21 14:36:14 -06:00
|
|
|
("ffg1156-1", 1): ["V30", None, "AA33", "AA34", "Y33", "Y34"],
|
|
|
|
("ffg1157-1", 1): ["AL33", None, "AN33", "AN34", "AK34", "AL34"],
|
|
|
|
("ffg1158-1", 1): ["C24", None, "A23", "A24", "B26", "A26"],
|
|
|
|
("ffg1926-1", 1): ["AK33", None, "AN34", "AN35", "AJ34", "AK34"],
|
|
|
|
("fhg1761-1", 1): ["AL36", None, "AM36", "AN36", "AJ36", "AJ37"],
|
|
|
|
("flg1155-1", 1): ["AL28", None, "AE28", "AF28", "AJ29", "AJ30"],
|
|
|
|
("flg1932-1", 1): ["V32", None, "T33", "R33", "U31", "T31"],
|
|
|
|
("flg1926-1", 1): ["AK33", None, "AN34", "AN35", "AJ34", "AK34"],
|
2017-08-08 11:16:35 -05:00
|
|
|
|
|
|
|
("ffva1156-2-e", 1): ["G26", None, "M20", "L20", "R21", "R22"],
|
|
|
|
("ffva1156-2-e", "sayma"): ["K21", None, "M20", "L20", "R21", "R22"],
|
2015-12-21 14:36:14 -06:00
|
|
|
}
|
|
|
|
|
2015-07-01 04:18:46 -05:00
|
|
|
pinouts = {
|
|
|
|
# bitstreams are named by die, package does not matter, speed grade
|
|
|
|
# should not matter.
|
2015-12-21 14:36:14 -06:00
|
|
|
#
|
|
|
|
# chip: (package, id, standard, class)
|
|
|
|
"xc3s100e": ("cp132", 1, "LVCMOS33", Spartan3),
|
|
|
|
"xc3s1200e": ("fg320", 1, "LVCMOS33", Spartan3),
|
|
|
|
"xc3s1400a": ("fg484", 1, "LVCMOS33", Spartan3A),
|
|
|
|
"xc3s1400an": ("fgg484", 1, "LVCMOS33", Spartan3A),
|
|
|
|
"xc3s1600e": ("fg320", 1, "LVCMOS33", Spartan3),
|
|
|
|
"xc3s200a": ("fg320", 2, "LVCMOS33", Spartan3A),
|
|
|
|
"xc3s200an": ("ftg256", 1, "LVCMOS33", Spartan3A),
|
|
|
|
"xc3s250e": ("cp132", 1, "LVCMOS33", Spartan3),
|
|
|
|
"xc3s400a": ("fg320", 2, "LVCMOS33", Spartan3A),
|
|
|
|
"xc3s400an": ("fgg400", 1, "LVCMOS33", Spartan3A),
|
|
|
|
"xc3s500e": ("cp132", 1, "LVCMOS33", Spartan3),
|
|
|
|
"xc3s50a": ("ft256", 1, "LVCMOS33", Spartan3A),
|
|
|
|
"xc3s50an": ("ftg256", 1, "LVCMOS33", Spartan3A),
|
|
|
|
"xc3s700a": ("fg400", 1, "LVCMOS33", Spartan3A),
|
|
|
|
"xc3s700an": ("fgg484", 1, "LVCMOS33", Spartan3A),
|
|
|
|
"xc3sd1800a": ("cs484", 1, "LVCMOS33", Spartan3A),
|
|
|
|
"xc3sd3400a": ("cs484", 1, "LVCMOS33", Spartan3A),
|
|
|
|
|
|
|
|
"xc6slx100": ("csg484-2", 1, "LVCMOS33", Spartan6),
|
|
|
|
"xc6slx100t": ("csg484-2", 1, "LVCMOS33", Spartan6),
|
|
|
|
"xc6slx150": ("csg484-2", 1, "LVCMOS33", Spartan6),
|
|
|
|
"xc6slx150t": ("csg484-2", 1, "LVCMOS33", Spartan6),
|
|
|
|
"xc6slx16": ("cpg196-2", 1, "LVCMOS33", Spartan6),
|
|
|
|
"xc6slx25": ("csg324-2", 1, "LVCMOS33", Spartan6),
|
|
|
|
"xc6slx25t": ("csg324-2", 1, "LVCMOS33", Spartan6),
|
|
|
|
"xc6slx45": ("csg324-2", 1, "LVCMOS33", Spartan6),
|
|
|
|
"xc6slx45t": ("csg324-2", 1, "LVCMOS33", Spartan6),
|
|
|
|
"xc6slx4": ("cpg196-2", 1, "LVCMOS33", Spartan6),
|
|
|
|
"xc6slx4t": ("qg144-2", 1, "LVCMOS33", Spartan6),
|
|
|
|
"xc6slx75": ("csg484-2", 1, "LVCMOS33", Spartan6),
|
|
|
|
"xc6slx75t": ("csg484-2", 1, "LVCMOS33", Spartan6),
|
|
|
|
"xc6slx9": ("cpg196-2", 1, "LVCMOS33", Spartan6),
|
|
|
|
"xc6slx9t": ("qg144-2", 1, "LVCMOS33", Spartan6),
|
|
|
|
|
|
|
|
"xc7a100t": ("csg324-1", 1, "LVCMOS25", Series7),
|
|
|
|
"xc7a15t": ("cpg236-1", 1, "LVCMOS25", Series7),
|
|
|
|
"xc7a200t": ("fbg484-1", 1, "LVCMOS25", Series7),
|
|
|
|
"xc7a35t": ("cpg236-1", 1, "LVCMOS25", Series7),
|
|
|
|
"xc7a50t": ("cpg236-1", 1, "LVCMOS25", Series7),
|
|
|
|
"xc7a75t": ("csg324-1", 1, "LVCMOS25", Series7),
|
|
|
|
"xc7k160t": ("fbg484-1", 2, "LVCMOS25", Series7),
|
|
|
|
"xc7k325t": ("fbg676-1", 1, "LVCMOS25", Series7),
|
2017-08-08 11:16:35 -05:00
|
|
|
"xc7k325t-debug": ("ffg900-1", 1, "LVCMOS25", Series7),
|
2015-12-21 14:36:14 -06:00
|
|
|
"xc7k355t": ("ffg901-1", 1, "LVCMOS25", Series7),
|
|
|
|
"xc7k410t": ("fbg676-1", 1, "LVCMOS25", Series7),
|
|
|
|
"xc7k420t": ("ffg1156-1", 1, "LVCMOS25", Series7),
|
|
|
|
"xc7k480t": ("ffg1156-1", 1, "LVCMOS25", Series7),
|
|
|
|
"xc7k70t": ("fbg484-1", 2, "LVCMOS25", Series7),
|
|
|
|
"xc7v2000t": ("fhg1761-1", 1, "LVCMOS18", Series7),
|
|
|
|
"xc7v585t": ("ffg1157-1", 1, "LVCMOS18", Series7),
|
|
|
|
"xc7vh580t": ("flg1155-1", 1, "LVCMOS18", Series7),
|
|
|
|
"xc7vh870t": ("flg1932-1", 1, "LVCMOS18", Series7),
|
|
|
|
"xc7vx1140t": ("flg1926-1", 1, "LVCMOS18", Series7),
|
|
|
|
"xc7vx330t": ("ffg1157-1", 1, "LVCMOS18", Series7),
|
|
|
|
"xc7vx415t": ("ffg1157-1", 1, "LVCMOS18", Series7),
|
|
|
|
"xc7vx485t": ("ffg1157-1", 1, "LVCMOS18", Series7),
|
|
|
|
"xc7vx550t": ("ffg1158-1", 1, "LVCMOS18", Series7),
|
|
|
|
"xc7vx690t": ("ffg1157-1", 1, "LVCMOS18", Series7),
|
|
|
|
"xc7vx980t": ("ffg1926-1", 1, "LVCMOS18", Series7),
|
2017-08-08 11:16:35 -05:00
|
|
|
|
|
|
|
"xcku040": ("ffva1156-2-e", 1, "LVCMOS18", Ultrascale),
|
|
|
|
"xcku040-sayma": ("ffva1156-2-e", "sayma", "LVCMOS18", Ultrascale),
|
2015-07-01 04:18:46 -05:00
|
|
|
}
|
|
|
|
|
2015-12-21 14:36:14 -06:00
|
|
|
def __init__(self, device, pins, std, toolchain="ise"):
|
2017-08-08 11:16:35 -05:00
|
|
|
ios = [self.make_spi(0, pins, std, toolchain)]
|
|
|
|
if device == "xc7k325t-ffg900-1": # debug
|
|
|
|
ios += [
|
|
|
|
("user_sma_clock_p", 0, mb.Pins("L25"), mb.IOStandard("LVCMOS25")),
|
|
|
|
("user_sma_clock_n", 0, mb.Pins("K25"), mb.IOStandard("LVCMOS25")),
|
|
|
|
("user_sma_gpio_p", 0, mb.Pins("Y23"), mb.IOStandard("LVCMOS25")),
|
|
|
|
("user_sma_gpio_n", 0, mb.Pins("Y24"), mb.IOStandard("LVCMOS25")),
|
|
|
|
]
|
|
|
|
xilinx.XilinxPlatform.__init__(self, device, ios, toolchain=toolchain)
|
|
|
|
|
|
|
|
@staticmethod
|
|
|
|
def make_spi(i, pins, std, toolchain):
|
|
|
|
pu = "PULLUP" if toolchain == "ise" else "PULLUP TRUE"
|
|
|
|
pd = "PULLDOWN" if toolchain == "ise" else "PULLDOWN TRUE"
|
2015-07-01 04:18:46 -05:00
|
|
|
cs_n, clk, mosi, miso = pins[:4]
|
2017-08-08 11:16:35 -05:00
|
|
|
io = ["spiflash", i,
|
|
|
|
mb.Subsignal("cs_n", mb.Pins(cs_n), mb.Misc(pu)),
|
|
|
|
mb.Subsignal("mosi", mb.Pins(mosi), mb.Misc(pu)),
|
|
|
|
mb.Subsignal("miso", mb.Pins(miso), mb.Misc(pu)),
|
|
|
|
mb.IOStandard(std),
|
|
|
|
]
|
2015-07-01 04:18:46 -05:00
|
|
|
if clk:
|
2017-08-08 11:16:35 -05:00
|
|
|
io.append(mb.Subsignal("clk", mb.Pins(clk), mb.Misc(pd)))
|
2015-07-01 04:18:46 -05:00
|
|
|
for i, p in enumerate(pins[4:]):
|
2017-08-08 11:16:35 -05:00
|
|
|
io.append(mb.Subsignal("pullup{}".format(i), mb.Pins(p),
|
|
|
|
mb.Misc(pu)))
|
|
|
|
return io
|
2015-07-01 04:18:46 -05:00
|
|
|
|
|
|
|
@classmethod
|
2017-08-08 11:16:35 -05:00
|
|
|
def make(cls, target, errors=False):
|
|
|
|
pkg, id, std, Top = cls.pinouts[target]
|
2015-12-21 14:36:14 -06:00
|
|
|
pins = cls.packages[(pkg, id)]
|
2017-08-08 11:16:35 -05:00
|
|
|
device = target.split("-", 1)[0]
|
2015-12-21 14:36:14 -06:00
|
|
|
platform = cls("{}-{}".format(device, pkg), pins, std, Top.toolchain)
|
2015-07-01 04:18:46 -05:00
|
|
|
top = Top(platform)
|
2017-08-08 11:16:35 -05:00
|
|
|
name = "bscan_spi_{}".format(target)
|
2015-07-01 04:18:46 -05:00
|
|
|
try:
|
2017-08-08 11:16:35 -05:00
|
|
|
platform.build(top, build_name=name)
|
2015-07-01 04:18:46 -05:00
|
|
|
except Exception as e:
|
2015-12-21 14:36:14 -06:00
|
|
|
print(("ERROR: xilinx_bscan_spi build failed "
|
2017-08-08 11:16:35 -05:00
|
|
|
"for {}: {}").format(target, e))
|
2015-07-01 04:18:46 -05:00
|
|
|
if errors:
|
|
|
|
raise
|
|
|
|
|
|
|
|
|
|
|
|
if __name__ == "__main__":
|
|
|
|
import argparse
|
|
|
|
import multiprocessing
|
|
|
|
p = argparse.ArgumentParser(description="build bscan_spi bitstreams "
|
|
|
|
"for openocd jtagspi flash driver")
|
|
|
|
p.add_argument("device", nargs="*",
|
|
|
|
default=sorted(list(XilinxBscanSpi.pinouts)),
|
|
|
|
help="build for these devices (default: %(default)s)")
|
|
|
|
p.add_argument("-p", "--parallel", default=1, type=int,
|
|
|
|
help="number of parallel builds (default: %(default)s)")
|
|
|
|
args = p.parse_args()
|
|
|
|
pool = multiprocessing.Pool(args.parallel)
|
|
|
|
pool.map(XilinxBscanSpi.make, args.device, chunksize=1)
|