2017-11-06 12:56:28 -06:00
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/*
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2019-10-27 13:48:25 -05:00
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* OpenOCD STM8 target driver
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* Copyright (C) 2017 Ake Rehnman
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* ake.rehnman(at)gmail.com
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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2017-11-06 12:56:28 -06:00
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*/
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#ifndef OPENOCD_TARGET_STM8_H
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#define OPENOCD_TARGET_STM8_H
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struct target;
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#define STM8_COMMON_MAGIC 0x53544D38
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#define STM8_NUM_CORE_REGS 6
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struct stm8_common {
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uint32_t common_magic;
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void *arch_info;
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struct reg_cache *core_cache;
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uint32_t core_regs[STM8_NUM_CORE_REGS];
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/* working area for fastdata access */
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struct working_area *fast_data_area;
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bool swim_configured;
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bool bp_scanned;
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uint8_t num_hw_bpoints;
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uint8_t num_hw_bpoints_avail;
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struct stm8_comparator *hw_break_list;
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uint32_t blocksize;
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uint32_t flashstart;
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uint32_t flashend;
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uint32_t eepromstart;
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uint32_t eepromend;
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uint32_t optionstart;
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uint32_t optionend;
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bool enable_step_irq;
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bool enable_stm8l;
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uint32_t flash_cr2;
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uint32_t flash_ncr2;
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uint32_t flash_iapsr;
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uint32_t flash_dukr;
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uint32_t flash_pukr;
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/* cc value used for interrupt flags restore */
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uint32_t cc;
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bool cc_valid;
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/* register cache to processor synchronization */
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int (*read_core_reg)(struct target *target, unsigned int num);
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int (*write_core_reg)(struct target *target, unsigned int num);
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};
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static inline struct stm8_common *
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target_to_stm8(struct target *target)
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{
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return target->arch_info;
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}
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const struct command_registration stm8_command_handlers[];
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#endif /* OPENOCD_TARGET_STM8_H */
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