50 lines
972 B
Prolog
50 lines
972 B
Prolog
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update=Tue 05 Dec 2017 16:16:45 AEST
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version=1
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last_client=kicad
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[cvpcb]
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version=1
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NetIExt=net
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[general]
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version=1
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[schematic_editor]
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version=1
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PageLayoutDescrFile=
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PlotDirectoryName=plots/
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SubpartIdSeparator=0
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SubpartFirstId=65
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NetFmtName=
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SpiceForceRefPrefix=0
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SpiceUseNetNumbers=0
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LabSize=60
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[pcbnew]
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version=1
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PageLayoutDescrFile=/home/user/code/keyboard_pcb/kicad_common/page_layouts/clear.kicad_wks
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LastNetListRead=
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PadDrill=1
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PadDrillOvalY=1
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PadSizeH=1.7
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PadSizeV=1.7
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PcbTextSizeV=1.5
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PcbTextSizeH=1.5
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PcbTextThickness=0.3
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ModuleTextSizeV=1
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ModuleTextSizeH=1
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ModuleTextSizeThickness=0.15
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SolderMaskClearance=0.03809999999999999
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SolderMaskMinWidth=0.0508
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DrawSegmentWidth=0.15
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BoardOutlineThickness=0.15
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ModuleOutlineThickness=0.15
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[eeschema]
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version=1
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LibDir=../kicad_common
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[eeschema/libraries]
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LibName1=power
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LibName2=device
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LibName3=conn
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LibName4=regul
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LibName5=libraries/atmel
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LibName6=libraries/connector
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LibName7=libraries/microchip
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LibName8=libraries/nordic
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