112 lines
3.3 KiB
Verilog
112 lines
3.3 KiB
Verilog
// SPDX-License-Identifier: AGPL-3.0-Only
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/*
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* Copyright (C) 2022 Sean Anderson <seanga2@gmail.com>
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*/
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`include "common.vh"
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module descramble (
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input clk,
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input [1:0] scrambled, scrambled_valid,
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input signal_status, test_mode,
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output reg locked,
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output reg [1:0] unscrambled, unscrambled_valid
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);
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reg locked_next;
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reg [1:0] ldd, unscrambled_next;
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reg [10:0] lfsr, lfsr_next;
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/*
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* The number of consecutive idle bits to require when locking, as
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* well as the number necessary to prevent unlocking. For the first
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* case, this must be less than 60 bits (7.2.3.1.1), including the
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* bits necessary to initialize the lfsr. For the second, this must be
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* less than 29 bits (7.2.3.3(f)). We use 29 to meet these requirements;
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* it is increased by 1 to allow for an easier implementation of the
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* counter, and decreased by 1 to allow easier implementation when
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* scrambled_valid = 2. The end result is that only 28 bits might be
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* required in certain situations.
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*/
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localparam CONSECUTIVE_IDLES = 5'd29;
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reg [4:0] idle_counter = CONSECUTIVE_IDLES, idle_counter_next;
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/*
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* The amount of time without recieving consecutive idles before we
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* unlock. This must be greater than 361us (7.2.3.3(f)). 2^16-1 works
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* out to around 524us at 125MHz.
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*/
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localparam UNLOCK_TIME = 16'hffff;
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/* 5us, or around one minimum-length packet plus some extra */
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localparam TEST_UNLOCK_TIME = 16'd625;
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reg [15:0] unlock_counter, unlock_counter_next;
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always @(*) begin
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ldd = { lfsr[8] ^ lfsr[10], lfsr[7] ^ lfsr[9] };
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unscrambled_next = scrambled ^ ldd;
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/*
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* We must invert scrambled before adding it to the lfsr in
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* order to remove the ^1 from the input idle. This doesn't
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* affect the output of the lfsr during the sample state
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* because two bits from the lfsr are xor'd together,
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* canceling out the inversion.
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*/
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lfsr_next = lfsr;
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if (scrambled_valid[0])
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lfsr_next = { lfsr[9:0], locked ? ldd[1] : ~scrambled[1] };
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else if (scrambled_valid[1])
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lfsr_next = { lfsr[8:0], locked ? ldd : ~scrambled };
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idle_counter_next = idle_counter;
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if (scrambled_valid[1]) begin
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if (unscrambled_next[1] && unscrambled_next[0])
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idle_counter_next = idle_counter - 2;
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else if (unscrambled_next[0])
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idle_counter_next = idle_counter - 1;
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else
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idle_counter_next = CONSECUTIVE_IDLES;
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end else if (scrambled_valid[0]) begin
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if (unscrambled_next[1])
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idle_counter_next = idle_counter - 1;
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else
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idle_counter_next = CONSECUTIVE_IDLES;
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end
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locked_next = 1;
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unlock_counter_next = unlock_counter;
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if (!idle_counter_next[4:1]) begin
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unlock_counter_next = test_mode ? TEST_UNLOCK_TIME : UNLOCK_TIME;
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/*
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* Reset the counter to 2 to ensure we can always
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* subtract idles without underflowing
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*/
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idle_counter_next = 2;
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end else if (|unlock_counter) begin
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unlock_counter_next = unlock_counter - 1;
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end else begin
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locked_next = 0;
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end
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end
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always @(posedge clk) begin
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unscrambled <= unscrambled_next;
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if (signal_status) begin
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lfsr <= lfsr_next;
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idle_counter <= idle_counter_next;
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unlock_counter <= unlock_counter_next;
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locked <= locked_next;
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unscrambled_valid <= scrambled_valid;
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end else begin
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lfsr <= 0;
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idle_counter <= CONSECUTIVE_IDLES;
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unlock_counter <= 0;
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locked <= 0;
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unscrambled_valid <= 0;
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end
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end
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`DUMP(0)
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endmodule
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