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ethernet
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WIP 100BASE-TX PHY
97 Commits 2 Branches 0 Tags 290 KiB
Verilog 50.1%
Python 46.8%
Makefile 2.3%
SystemVerilog 0.8%
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Sean Anderson fb588994b7 tb: phy_core: Fix col/crs detection 
Detecting non-clock signal edges with RisingEdge and FallingEdge is not
very robust, and is recommended against. Track edges manually.

Fixes: f6f3f02 ("Add phy_core")
Signed-off-by: Sean Anderson <seanga2@gmail.com>
 		2023-01-09 20:50:00 -05:00
LICENSES Add licenses 2022-11-05 12:50:12 -04:00
rtl pmd: Initialize sd_delay 2023-01-09 20:31:39 -05:00
tb tb: phy_core: Fix col/crs detection 2023-01-09 20:50:00 -05:00
.gitignore Add some more files to gitignore 2022-11-05 12:52:57 -04:00
4b5b.gtkw Initial commit 2022-05-23 20:57:03 -04:00
CONTRIBUTING Add licenses 2022-11-05 12:50:12 -04:00
COPYING Add licenses 2022-11-05 12:50:12 -04:00
Makefile Add DP83223-based PMD 2022-11-30 18:14:23 -05:00