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ethernet
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WIP 100BASE-TX PHY
12 Commits 2 Branches 0 Tags 290 KiB
Verilog 50.1%
Python 46.8%
Makefile 2.3%
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Sean Anderson fafce4df00 pmd: Use correct SB_IO clock names 
The clock signals are not named correctly. Fix this.

Fixes: 1d65661 ("Add pmd")
Signed-off-by: Sean Anderson <seanga2@gmail.com>
 		2022-08-06 21:47:21 -04:00
rtl pmd: Use correct SB_IO clock names 2022-08-06 21:47:21 -04:00
tb tb: pcs: Send packet spacing packets immediately 2022-08-06 21:47:21 -04:00
.gitignore Initial commit 2022-05-23 20:57:03 -04:00
4b5b.gtkw Initial commit 2022-05-23 20:57:03 -04:00
Makefile Initial commit 2022-05-23 20:57:03 -04:00