80 lines
1.4 KiB
Verilog
80 lines
1.4 KiB
Verilog
// SPDX-License-Identifier: AGPL-3.0-Only
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/*
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* Copyright (C) 2022 Sean Anderson <seanga2@gmail.com>
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*/
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`include "common.vh"
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`include "io.vh"
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`timescale 1ns/1ps
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module pmd_dp83223 (
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input clk_250,
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input clk_125,
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/* I/O */
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input indicate_data,
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input signal_detect,
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output reg request_data,
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/* "PMD" */
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input tx_data,
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output [1:0] rx_data,
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output [1:0] rx_data_valid,
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output reg signal_status,
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/* Control */
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input loopback
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);
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wire tx_nrzi;
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nrzi_encode encoder (
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.clk(clk_125),
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.nrz(tx_data),
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.nrzi(tx_nrzi)
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);
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`ifdef SYNTHESIS
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SB_IO #(
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.PIN_TYPE(`PIN_OUTPUT_ALWAYS | `PIN_OUTPUT_REGISTERED),
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) tx_data_pin (
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.PACKAGE_PIN(request_data),
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.OUTPUT_CLK(clk_125),
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.D_OUT_0(loopback ? 1'b0 : tx_nrzi)
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);
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`else
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always @(posedge clk_125)
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request_data <= loopback ? 1'b0 : tx_nrzi;
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`endif
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wire signal_status_nrzi;
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wire [1:0] rx_nrzi, rx_nrzi_valid;
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pmd_dp83223_rx rx (
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.clk_125(clk_125),
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.clk_250(clk_250),
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.signal_detect(signal_detect),
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.indicate_data(indicate_data),
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.signal_status(signal_status_nrzi),
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.rx_data(rx_nrzi),
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.rx_data_valid(rx_nrzi_valid)
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);
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nrzi_decode decoder (
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.clk(clk_125),
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.rst(loopback ? 1'b0 : !signal_status_nrzi),
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.nrzi(loopback ? { tx_nrzi, 1'bX } : rx_nrzi),
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.nrzi_valid(loopback ? 2'b01 : rx_nrzi_valid),
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.nrz(rx_data),
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.nrz_valid(rx_data_valid)
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);
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initial signal_status = 0;
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always @(posedge clk_125)
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signal_status <= loopback ? 1'b1 : signal_status_nrzi;
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endmodule
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