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WIP 100BASE-TX PHY
15 Commits 2 Branches 0 Tags 290 KiB
Verilog 50.1%
Python 46.8%
Makefile 2.3%
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Sean Anderson e79807cdff tb: pmd: Ensure signal_detect starts low 
To make sure that pmd.signal_status comes up at the right time, keep
signal_detect low at the start of simulation. We don't need to set
pmd.rx, because X is the default value (or rather Z is, but it's the
same for our purposes).

Fixes: 1d65661 ("Add pmd")
Signed-off-by: Sean Anderson <seanga2@gmail.com>
 		2022-08-06 21:47:21 -04:00
rtl pcs: Fix incorrect assignment type 2022-08-06 21:47:21 -04:00
tb tb: pmd: Ensure signal_detect starts low 2022-08-06 21:47:21 -04:00
.gitignore Initial commit 2022-05-23 20:57:03 -04:00
4b5b.gtkw Initial commit 2022-05-23 20:57:03 -04:00
Makefile Initial commit 2022-05-23 20:57:03 -04:00