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ethernet
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WIP 100BASE-TX PHY
115 Commits 2 Branches 0 Tags 290 KiB
Verilog 50.1%
Python 46.8%
Makefile 2.3%
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Sean Anderson e59e34db93 tb: Fix reset occasionally failing 
We might not release rst synchronously if clk was already high. Fix this
by forcing clk to z.

Fixes: 19f2f65 ("axis_mii_tx: Add reset")
Signed-off-by: Sean Anderson <seanga2@gmail.com>
 		2023-01-14 00:05:35 -05:00
LICENSES Add LFSR 2023-01-09 21:01:27 -05:00
lib Add LFSR 2023-01-09 21:01:27 -05:00
rtl axis_mii_tx: Don't reset mii_txd 2023-01-13 23:35:23 -05:00
tb tb: Fix reset occasionally failing 2023-01-14 00:05:35 -05:00
.gitignore Add some more files to gitignore 2022-11-05 12:52:57 -04:00
.gitmodules Add LFSR 2023-01-09 21:01:27 -05:00
4b5b.gtkw Initial commit 2022-05-23 20:57:03 -04:00
CONTRIBUTING Add licenses 2022-11-05 12:50:12 -04:00
COPYING Add licenses 2022-11-05 12:50:12 -04:00
Makefile Add LFSR 2023-01-09 21:01:27 -05:00