76 lines
1.4 KiB
Verilog
76 lines
1.4 KiB
Verilog
// SPDX-License-Identifier: AGPL-3.0-Only
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/*
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* Copyright (C) 2022 Sean Anderson <seanga2@gmail.com>
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*/
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`include "common.vh"
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module top (
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input clk_100,
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/* DP83223 */
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input [3:0] indicate_data,
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input [3:0] signal_detect,
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output [3:0] request_data,
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/* LEDs */
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output collision, transmitting,
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/* These match the names on the PCB which I am too lazy to change. */
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output [3:0] link_act,
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output [3:0] speed,
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/* Unused for the moment */
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input [3:0] polarity,
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output [3:0] loopback
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);
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wire clk_125, clk_250;
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SB_PLL40_2F_CORE #(
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.FEEDBACK_PATH("SIMPLE"),
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.DIVR(4'd0),
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.DIVF(7'd9),
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.DIVQ(3'd2),
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.FILTER_RANGE(3'd5),
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.PLLOUT_SELECT_PORTB("GENCLK_HALF")
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) pll (
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.REFERENCECLK(clk_100),
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.PLLOUTGLOBALA(clk_250),
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.PLLOUTGLOBALB(clk_125),
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.BYPASS(1'b0),
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.RESETB(1'b1)
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);
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reg collision_raw, transmitting_raw;
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reg [3:0] receiving;
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hub #(
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.WISHBONE(0),
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.PORT_COUNT(4)
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) hub (
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.clk_125(clk_125),
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.clk_250(clk_250),
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.indicate_data(indicate_data),
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.signal_detect(signal_detect),
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.request_data(request_data),
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.wb_cyc(1'b0),
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.wb_stb(1'b0),
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.collision(collision_raw),
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.transmitting(transmitting_raw),
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.link_status(speed),
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.receiving(receiving)
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);
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led_blinker #(
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.LEDS(6)
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) blinker(
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.clk(clk_125),
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.triggers({ collision_raw, transmitting_raw, receiving}),
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.out({ collision, transmitting, link_act}),
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.test_mode(1'b0)
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);
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assign loopback = 4'b0;
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endmodule
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